Hello, This is a topic that interest me greatly as well. Some of the work we have done uses a digital frequency tracking loop to generate frequency errors directly from sampled data using a sampling system and ethernet system of our own design. We opted for using a look-up table-based DDS in the final frequency conversion to baseband (you mentioned considering CORDIC) and CIC filters/decimation..all in FPGA (Altera Cyclone III). This was done for testing two-way coherent transponders. See a description here<https://www.researchgate.net/publication/332241644_Coherent_tracking_error_characterization_in_microwave_transponders>.
Yes, it seems to me that a band limiting filter on the input would be absolutely necessary, since the sampling BW of the ADC is so high. Also, run ADCs at full sampling rate, then use low pass filtering (Hogenauer/CIC filters?) with decimation in the digital domain. You will get extra bits of resolution that correspond to the effective oversampling (ADC SPS / Decimated SPS) possibly allowing a smaller ADC word width. Raspberry Pi is your friend in a project like this! We used a dsPIC series processor in our work because we already had an ethernet interface already up and running on this device and all the chips are hand-solderable (TQFP instead of BGA). Looks like a great project. I will be lurking around when you post updates! Cheers, Bill On 01.09.19 17:49, AC0XU (Jim) wrote: Jan-Derk- Excellent and exciting work! Thanks for sharing with the newsgroup... I have a couple of questions: 1. The input bandwidth of the digitizer chip is 750 MHz (very impressive), but what happens to input noise that is aliased? When sampling at 10MHz (plus offset) everything above 5MHz is aliased. Doesn't this suggest that high performance bandpass filters on the input, for whatever frequencies are of interest, would be helpful when measuring time stability (but not phase noise)? I suppose it as a question of noise/instability added by the filter vs. noise removed from the input by the filter, and I haven't seen a published analysis of this... 2. You mentioned that you are decimating the data to get the sample rate down. Doesn't this raise the noise floor above what it could be if all the samples were processed? 3. What algorithm are you using for the digital ZCD? 4. How hard would it be to put an Ethernet interface on the output? Would it be easier to attached the device to a Raspberry Pi or sim as a USB-to-Ethernet converter? In my lab I find USB to be annoyingly problematic, and prefer Ethernet... I have been experimenting with DDMTD setups using commercial 14- and 16-bit simultaneous-sampling digitizer boards, and processing the phase data at the full rates (from a few MHz to 250 MHz or so sample rate) by correlation method instead of ZCD. The results have been o.k. but not quite as good as I was hoping for. There is a complex relationship between the sample rate and performance which I haven't quite worked out. Also, the number-crunching takes a while on conventional PC. Thanks- Jim Jim _______________________________________________ time-nuts mailing list -- [email protected]<mailto:[email protected]> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
