Hi Unless the 100 MHz “VCO” is an OCXO, it is going to be tough to keep things locked at a fractional Hz sort of bandwidth. It’s simply a matter of how much the phase / frequency is likely to change while you are trying to get it to lock / keep it locked. Things like shock and vibration get into it along with temperature.
There’s nothing “magic” about digital vs analog. You do the same things with both. Gain margin / phase margin / damping matter in any control loop. Both approaches run into side issues with things like divider and phase detector noise floors. You may need a wide bandwidth loop to get things lined up and a soft switchover ( = no spikes ) to a narrower bandwidth. You see that done in GPSDO’s a lot. Plenty of grubby details to deal with ….. Bob > On Nov 19, 2019, at 4:48 AM, mar...@ptsyst.com wrote: > > > > Hello, > > > > Have anyone had any luck designing a phase lock loop with very small > bandwidths, e.g. less than 0.2 Hz. > > > > I need to lock a 100 MHz Ultra low oscillator to a 10 MHz ultra low > oscillator and I need a loop bandwidth less than 0.2 Hz. > > > > Quartzlock do a digital PLL board with bandwidths to 1 mHz. However I never > got it to work. > > > > The 10 MHz reference has phase noise of -116 dBc/Hz at 1Hz offset. The 100 > MHz VCO make -104 at 1 Hz. > > > > Obviously I'm trying to preserve the 100 MHz phase noise. > > > > Any advice would be appreciated. > > > > Best Regards > > Martyn > > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.