> To a first order, the ADC is like an ideal multiplier/mixer - phase noise on > the > clock contributes to phase noise on the sampled data by reciprocal mixing, > just > like a mixer.
The ADC-as-mixer metaphor is a useful abstraction, but a leaky one. Here's the way I think of it: while all mixers are multipliers, they fall into two distinct categories, 'stateful' and 'stateless.' Conventional mixers are switches with no internal state of their own. At any given moment they are either on or off based on the LO input state, or they exhibit forward or reverse conduction in the case of a diode ring or similar balanced structure. So their ideal response is dictated solely by the usual Fourier expansion of the square-wave LO harmonics including the first. A harmonic mixer is another stateless mixer, but through topology and component selection it is designed to respond best to input signals near even, odd, or (if driven by a comb generator) both multiples of the LO frequency. Still subject to Fourier at the end of the day, but with specific workarounds where needed. Now, while a sampler is still a multiplier at heart, some 'state' in the form of charge on the sample/hold capacitor is retained from one LO cycle to the next. As a result, unlike a conventional mixer, a sampler's theoretical response at higher input frequencies has nothing to do with the Fourier content of the LO drive signal, but is instead limited by the hold capacitance and external source impedance. It ends up looking like a sin(x)/x function, falling off slowly in general with input frequency but with periodic zeroes near LO harmonics >1. One consequence of charge retention is that when the input signal is in the first Nyquist zone, meaning below fLO/2, no net frequency translation occurs in a sampler. There is no mixing going on, hence no reciprocal mixing either. The sampler's zero-order hold characteristic passes the captured input signal straight through to the output. Because your ADC's front end is a sampler, this is the condition that applies when you digitize a 10 MHz input signal with a 122.88 MHz clock. About 13 times per input cycle, a sample of the 10 MHz signal is captured and transferred to the hold capacitance for eventual readout on the data bus. Any jitter that's present on the 122.88 MHz clock will be transferred as well, but it will be attenuated by 20*log10(12.288) dB because each clock cycle is responsible for capturing only about 1/13 of each input cycle. Make sense? -- john, KE5FX Miles Design LLC _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
