But you don't need a DDS route to get 1 PPS from any frequency that is an exact multiple of 1Hz. I clock a PIC with 10MHz from a master reference. An interrupt is generated at an exact submultiple of this, and additional code outputs a pulse every 250000 clocks (clock freq = Fosc / 4)
Or from 10MHz, four 74AC390 CMOS counters will do it Or am I missing some fundamental issue here? Andy www.g4jnt.com On Mon, 22 Nov 2021 at 18:20, Gerhard Hoffmann <g...@hoffmann-hochfrequenz.de> wrote: > > > Am 22.11.21 um 18:31 schrieb Erik Kaashoek: > > Some time ago I needed a output at 10,000000.001Hz so I tried to do that > > with a SI5351. > > Using pure integer math (as the PLL and divider register are integers) i > > search for a combination of 3 divider/multipliers that gave the least > > error. > > If the reference frequency is not integer related to the internal PLL > > frequency and multiplier/divider registers you always will have limited > > accuracy as there is a fractional error. > > The amount of error will depend on the number of digits in the > > multiplier/divider register lengths and the care you take to search for > > the best solution. > > If the DDS has a PLL driven clock this could be the cause. > > There once was a BCD DDS chip made by Standard Telecom. > Doing that in an FPGA would be an easy exercise. > > Cheers, Gerhard > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send > an email to time-nuts-le...@lists.febo.com > To unsubscribe, go to and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send an email to time-nuts-le...@lists.febo.com To unsubscribe, go to and follow the instructions there.