Hi As noted in those app notes, there is a lot more to what goes on with an ADC than a single spot noise spec would cover. Those grubby details do indeed impact what sort of signal source makes sense and how it limits system performance.
Sine to square conversion is always a bit messy. It is unlikely one will find a < -120 dbc / Hz @ 1 Hz 10 MHz OCXO with a square wave output. Like it or not, we live in a digital world. Simply converting the sine to square and preserving that sort of noise level is going to be a challenge. My only concern here is that before one goes of and spends 5,10, or 20 thousand dollars on an OCXO, some of these details get talked through. Also doing this sort of design without a bench set up to measure these noise levels accurately is very risky. When you get to these levels it becomes a “measure everything” sort of process. How good *is* an OCXO spec’d at < -120 dbc likely to need to be? If it’s a production part, they should be coming in at -123 to -126 to make it a buildable spec. Any closer than that and yield goes to zero when this or that very minor issue comes up. We love to look at plots showing 120.01 dbc and say “that does it”. In a production environment, not so much. You need some margin. If you can’t do a design that has some margin, then it becomes a selection process. You build a thousand and test them all. Out come three pieces. The cost of testing the other 997 all has to go into the price of those three. If there is no market for the other 997, then the cost of throwing them away also gets loaded into the 3 good ones. If it takes two years to find those three, the delivery will likely be overdue …. When you do find the magic 3, what happens if you wait a week / month and retest them? Hmmm ….. maybe we shouldn’t have done that …. yikes …. Getting accurate repeatable data at 1Hz offset is a very long and drawn out process. Again a reason for needing that margin ….. Bob > On Jan 10, 2022, at 1:19 PM, Lux, Jim <[email protected]> wrote: > > On 1/10/22 9:56 AM, Bob kb8tq wrote: >> Hi >> >> An equally important part of this: >> >> What are you driving with this OCXO and what is it’s measured noise floor >> at 1 Hz (or 10 Hz or what ever ….). In some cases a “crazy” OCXO is actually >> quieter than the device it is driving. That means that the last 5 or 10 db >> in phase >> noise improvement really has zero impact on the system performance. I’ve run >> into this a *lot* of times over the years. >> >> Bob > > This comes up a lot with ADCs.. Wideband driver amplifiers on the clock > inputs may put more noise on the digitized signal. > > > An-756 from Analog Devices > > Sampled Systems and the Effects of Clock Phase Noise and Jitter > > > https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf > > and > Clocking the RF ADC: Should you worry about jitter or phase noise? > > https://www.ti.com/lit/an/slyt705/slyt705.pdf > > _______________________________________________ > time-nuts mailing list -- [email protected] -- To unsubscribe send an > email to [email protected] > To unsubscribe, go to and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] -- To unsubscribe send an email to [email protected] To unsubscribe, go to and follow the instructions there.
