I found a commercial programmable GPSDO that looks like it would do the
job. Based on a Si chip.
http://leobodnar.com/files/Informal%20Evaluation%20of%20a%20Leo%20Bodnar%20GPS%20Frequency%20Reference.pdf
Performance is not in the "great" category but I am guessing it would be
in the "good enough" category. And it does not require any design work
or project construction time.
73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com
On 4/4/22 7:36 AM, Bob kb8tq wrote:
Hi
For a variety of reasons, you will have a loop bandwidth in the > 10 Hz
to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
after multiplication) should be as good / better. Even with some work,
the VCXO still will wander around due to temperature. Unless you go
crazy, it also will wander a bit from supply. There’s also the chance of
vibration or shock.
As mentioned in another post, component values on an properly designed
analog loop running one of the typical chips get pretty crazy at very low
loop bandwidths. You now get into questions about sensitivity of components
if you go with certain ceramics, leakage if you run an electrolytic, and with
size if you go with something else.
Bandwidth and damping ( or phase margin ) are two independent variables
when you design a PLL. You can have a narrowband bandwidth and a lot
of damping or the same bandwidth without much damping. It’s all in the
design equations ….
Bob
On Apr 3, 2022, at 11:22 PM, Jeff Blaine <[email protected]> wrote:
It looks like the XO version is mounted on the PCB. But there is a VCXO
version which would run about +/- 35 PPM/3.3V typical and that's (amazingly)
available.
Since this EFT is not an on-board capability, at the moment, I'm thinking to
mount the VCXO - and associated goodies to slave it to the 10 Mhz GPSDO feed -
in a separate enclosure that could allow the VCXO to be thermally insulated.
The temp swing vs. time will move very slowly and that would allow a very
damped PLL loop to apply corrections.
I've not done anything with a PLL before but I don't envision this as being too complicated. And
it would be a pretty cool project. Don't need true "phase" lock, but rather
"frequency control" without degrading the noise characteristics of the VCXO.
73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com
On 4/3/22 7:38 PM, Lux, Jim wrote:
On 4/3/22 5:09 PM, Bob kb8tq wrote:
Hi
Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.
Bob
And what about moving off the board - so you don't have to chase the
temperature swings.
On Apr 3, 2022, at 7:57 PM, Jeff Blaine <[email protected]> wrote:
I've got a couple of Red Pitaya 122-16 SDR and want to discipline them to an
external low noise GPSDO source. Wanted to see if there were some easy
solutions that fell into this category.
For the prior generation (QS1R), I had built a homebrew OCXO based on a custom
low noise crystal from ICM and that worked great for the 125 Mhz application.
Unfortunately this Pitaya is a bit removed in Fc and ICM has been out of biz
for several years now.
The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 which runs
about -115 dBc/hz at 100 Hz spacing and that's probably not a limitation for
the unit. Unfortunately the OSC is a bit too sensitive to external temp and
wanders around quite a lot (+/- 5 PPM) compared to the homebrew OCXO - over the
annual ambient temp range of (10-35C) (all datasheet referenced values). The
Abracon unit is mounted on the board with the FPGA and sees additional temp
range depending on other heat generation factors (FPGA loading).
I have a couple of commercial GPSDO on the bench now, so a pretty clean 10 Mhz GPSDO
reference is available now. And I've seen enough board discussion to know that a
homebrew GPSDO solution is one of those "it's harder than it looks" things.
Hence the desire just to buy whatever is the silver bullet, as long as it does not
require too much silver. ha ha
Appreciate any suggestions. TKs!
73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com
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