Hi Shivam, Firstly, you should reach out to the OpenSoCDebug folk at http://opensocdebug.org/ - This is the group that is working on a new replacement for the openrisc's Advance Debug System which should work on things like RISC-V. It is likely they will have a lot of advice on how to proceed.
On 11 March 2018 at 06:58, SHIVAM AGGARWAL <shivam16...@iiitd.ac.in> wrote: > Hi, > > I have successfully set up the development environment. Here’s the link: > https://pasteboard.co/HboNPNB.png > > I am currently reading about issue #39 > <https://github.com/timvideos/getting-started/issues/39>, to create a > generic debug interface for soft-CPU cores and connect to GDB. > > Progress so far > > > 1. > > I read about advanced debug system from openCores > <https://opencores.org/usercontent,doc,1270062172>. The document > elaborates the debugging system for OpenRisc-1000 Based systems. The > document provides information to support debugging both during simulation > as well as directly on the hardware. > 2. > > I also read about JTAG and wishbone specifications. > > > > The doc illustrates the following diagram to build hardware level > debugging system. > > There are a couple of issues with this diagram. Please take another look at the diagram already supplied in issue #39. Unlike most system, thanks to LiteX we already have the ability to connect the wishbone bus inside our FPGA to a host computer via a bunch of different protocols (uart, Ethernet, PCIe, etc). This means we don't need a lot of the functionality found in the adv_debug_sys -- we can already read/write any memory region and control the FPGA peripherals registers. The parts which are missing are; (a) A subsystem inside the FPGA which has the ability to control the CPU cores (b) The software on the host which allows gdb to communicate with this new subsystem via our *existing* wishbone bridge. These are shown in blue on the diagram in issue #39 and as the "Detail Explanation" section <https://github.com/timvideos/getting-started/issues/39#Detailed%20Explanation> says, *The student will need to implement the parts shown in blue in the following diagram;* > > Queries: > > 1. > > Is it acceptable to re-use the above approach implemented by OpenCores > given in the attached document? > > No. If we wanted to use the approach implemented by opencores, we would just be using the existing system. > > 1. > > Do we need support for multiple softCPU cores at the same time? Can we > use a MUX to switch between different softCPU cores? > > Only one softCPU will be inside the FPGA at one time. The important part is that we can load gateware onto the FPGA with different soft CPUs at *different times* and we want the debug system to be compatible with all these different soft CPUs. > > 1. > > After looking at the schematic of Numato Opsis board, I think standard > JTAG TAP implementation is used. Is that correct? > > I'm not sure what you mean by "standard JTAG TAP" -- the Opsis is a bit strange regarding how JTAG is used on it. However, this detail is *not important* to this project as the debug core should be not care about the protocol used to talk to the debug interface inside the FPGA -- this is all already taken care of by the LiteX bridge. (FYI - On the Opsis we would generally be using the Gigabit Ethernet interface.) > > 1. > > Do I need to implement the project in Migen? > > Correct. > > 1. > > I also looked at the documentation of OpenOCD but couldn’t understand > how it will be used for the project. Any help on that part? > > OpenOCD has the ability to talk to control the or1k inside the FPGA via the JTAG interface, so this could be a place for inspiration. > Things to do: > > > 1. > > To look into the internal working of each module. How each module will > interact with one another? > > Hopefully I've provided the feedback you need above. > > 1. > > How to build an efficient system to support multiple soft-CPU cores? > > This is not needed. This project is about create a system which can work with multiple different soft-CPU architectures -- not about supporting multiple soft-CPU cores at same time. You can think of this more like writing software which works both on a mobile phone and a desktop computer. Hope that helps! Tim 'mithro' Ansell -- You received this message because you are subscribed to the Google Groups "Tim Videos - timvideos.us" group. To unsubscribe from this group and stop receiving emails from it, send an email to timvideos+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
