I would need to read the AVR External Interrupts section (again...) to
be completely sure, but I believe level triggered ints will only
last for the time that the level exists. Edge triggered ints will
persist until cleared, so you won't miss them. In either case there
will be some response time jitter which could be minimized with
careful interrupt handling, which is what makes a real Real Time OS
so much fun to design and build.
As to your previous question about using semaphores of some kind instead
of blocking interrupts in atomic{} sections...Yah Shure Ya Betcha...
However no one has implemented mutexes in TOS because it seems that
the atomic thing works pretty well. Also I don't see a test-set-branch
instruction in the AVR, so you would have to block ints for a short
period to implement the basic mutex anyway.
Do you have a requirement for minimum/predictable interrupt response time?
MS
Adam wrote:
If an hardware interrupt is blocked by an atomic section, will the interupt
be re-issued after "enableInterupt" (upon completion of atomic section)? It
seems related to hardware and OS implementation -- please comment.
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