Like I said....read the External Interrupts section of the ATMEGA manual...
But my belief is that the internally generated interrupts, e.g., UART, are
edge triggered, and thus persist until cleared. If you are in a section
of code where interrupts are disabled, and you do not clear the pending
int, you will receive a new int one instruction after re-enabling (the one
instruction thing is is well buried in the manual).
As long as you don't go re-enabling interrupts on your own (which is
basically ending the atomic{} block), pending edge-triggered ints will
be deferred for ever. You may miss subsequent interrupts if you don't
free things up quickly enough, but the last one will still be there.
The addenda from John Regehr about re-enabling inside interrupt handlers
is true, and a really...stupid would be a good but pejorative word...
thing to do in a system that doesn't have multiple interrupt levels.
But it is not relevant to atomic sections.
MS
Adam wrote:
I am not familiar with the difference of "level triggered ints" and "edge
triggered ints". Anyway, is the second case used in MicaZ harware interupt?
If this is the case where interupt can be defered, then I will be okay with
that atomic is implemented through disbling interrupt.
Please confirm this.
-----Original Message-----
From: Michael Schippling [mailto:[EMAIL PROTECTED]
Sent: Thursday, September 07, 2006 12:44 PM
To: Adam
Cc: 'tinyos-help'
Subject: Re: [Tinyos-help] Interupt in MicaZ and TelosB
I would need to read the AVR External Interrupts section (again...) to be
completely sure, but I believe level triggered ints will only last for the
time that the level exists. Edge triggered ints will persist until cleared,
so you won't miss them. In either case there will be some response time
jitter which could be minimized with careful interrupt handling, which is
what makes a real Real Time OS so much fun to design and build.
As to your previous question about using semaphores of some kind instead of
blocking interrupts in atomic{} sections...Yah Shure Ya Betcha...
However no one has implemented mutexes in TOS because it seems that the
atomic thing works pretty well. Also I don't see a test-set-branch
instruction in the AVR, so you would have to block ints for a short period
to implement the basic mutex anyway.
Do you have a requirement for minimum/predictable interrupt response time?
MS
Adam wrote:
If an hardware interrupt is blocked by an atomic section, will the
interupt be re-issued after "enableInterupt" (upon completion of
atomic section)? It seems related to hardware and OS implementation --
please comment.
_______________________________________________
Tinyos-help mailing list
[email protected]
https://mail.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help
_______________________________________________
Tinyos-help mailing list
[email protected]
https://mail.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help
