The problem does seem to be with reset/interrupt in the watchdog timer
for the Atmega 1281. I've explicitly cleared the interrupt bit in
HardwareC.nc and it seems to produce a proper reboot sequence. (It
doesn't seem to be copying the image correctly, but baby steps along the
way ...) Here's the fleck3b HardwareC.nc that I'm using
module HardwareC {
provides {
interface Hardware;
}
}
implementation {
command void Hardware.init() {
MCUSR = 0;
wdt_disable();
WDTCSR &= ~WDIE;
}
command void Hardware.reboot() {
wdt_disable();
WDTCSR &= ~WDIE;
wdt_enable(1);
}
}
and the NetProg_platform.h now has
void netprog_reboot() {
wdt_disable();
WDTCSR &= ~WDIE;
wdt_enable(1);
while (1);
}
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