Hi all, I am trying to minimize the latency while transmitting without loading the packet in advance.
First, half of the packet is loaded using SpiPacket interface as usual, and I issue STXON command. And then the rest of the packet is loaded using TXFIFO_RAM interface to specify the offset in the TXFIFO. But during this TXFIFO_RAM.write() operation, a TX underflow occurs. CC2420 is sending some signal that is invisible to the sniffer. In theory, this must work since SPI is faster than RF. Am I doing something wrong here, or the TXFIFO not accessible at all during transmission? Thanks in advance! Jung Il
_______________________________________________ Tinyos-help mailing list [email protected] https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help
