tank121;686127 Wrote: > the SPDIF is outputted > directly from the freescale processor without re- > synchronisation (the SPDIF is not re- latched to > the clean audio clock). >
This is simply not true, the S/PDIF stream from the processor goes to a flip-flop which reclocks it from the local clock. There are two oscillators, one for the 44.1 family and one for the 48 family. The output from these two oscillators goes to a mux which selects the correct one for the sample rate currently playing, then the output of the mux goes to the clock pin of a flip-flop that reclocks the S/PDIF stream. The output from the flop goes through a network of a few resistors and cap and out to the RCA jack. The SB3 does NOT do this, it outputs the S/PDIF stream from an FPGA to a buffer and to the output. Maybe John was thinking about the SB3. >From my measurements of the clock it is around 35ps at the clock pin of the flop, I can't directly measure the actual digital output, I don't have the right tool for that, but I really doubt its 1ns. The flop used to reclock the stream is a very good choice for the job (exactly the same one I use in my DACs), there is no way its going to be adding that much jitter. John S. -- JohnSwenson ------------------------------------------------------------------------ JohnSwenson's Profile: http://forums.slimdevices.com/member.php?userid=5974 View this thread: http://forums.slimdevices.com/showthread.php?t=93227 _______________________________________________ Touch mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/touch
