On Tue, 2008-05-27 at 21:37 +1000, Brett Nash wrote: > > > > Actually that is rather odd. You shouldn't be getting bus errors on an > > Intel platform as it can do non-aligned accesses. > > Umm.. Only if the Unaligned bit is set in the flags register. Any OS > designed with half a clue or an application writer with half a clue and > some knowledge of CPU usage will turn that bit off.
> Apple turn it off by default I do believe (god bless them). The CPU > itself boots with it off ;-) Well, they don't have fixups on PPC, so I guess there is not reason to have them on Intel too :) > Unaligned loads are handled by microcode BTW, they actually expand to > two (independent) loads, two shifts and a register copy. They are one > of the reasons intel CPUs need stupid guarantees on TLB entries (the > last _NINE_ entries are never flushed). Any idea how to get a userspace application in Intel Linux to not have fixups automatically? (And hence we can share the pain too.) > > It will be interesting to find out what is going wrong. > > /me notes it's probably unaligned access after a string. Interestingly, it's not in a function I would have thought would have these types of accesses. Tim 'Mithro' Ansell _______________________________________________ tp-devel mailing list [email protected] http://www.thousandparsec.net/tp/mailman.php/listinfo/tp-devel
