Hello TREG'rs, I'm having difficulty designing a UK holding circuit on a PC card. The difficulty is caused by two I-V templates. One is from NET 4 and the other from TBR 21. The holding circuit for each template is different. The template from NET 4, 4.5 DC characteristics (Figure 1) has soft current limiting, linearly dropping from 60 mA at 40V to 125 mA at 0V.
The TBR 21 template Figure 4: (TE voltage/current characteristics) has 60 mA brick wall current limiting. It drops straight down from 36.2V to 0V. To meet NET 4 template causes the holding circuit darlington transistor to generate a large amount of heat. I don't think a PC card will not survive long under those conditions. I have a design using FET's which works well, but using FET's is not possible. I know from past experience a FET holding circuit cannot be used in a V.34 design. They kill V.34 receiver performance in a certain percent of manufactured modems (About 12%). Does anyone know which template is the correct one to use? Thank you in advance. Regards, Duane Marcroft Telecom Consultant
