Hi Fellow Embedded Enthusiasts:
I was following the recent posts about RISC-V. It is a powerful force in low
end micro space, but it is not limited to that? What about a large number of
RV32 processors in a very large FPGA fabric. The idea of creating custom
instructions is particularly intriguing since it exploits the configurability
of FPGA's. If a fixed function ASIC solves the problem, send a check to
Nvidia, if not deploy a FPGA. I don't think we will scare Jensen Huang either
way. :-)
Initial Hardware Baseline:
The initial thought might be to go with Xilinx/AMD FPGA for performance, an
older Ultrascale/Ultrascale+ part, but I am going to use a Microchip part for
this project.
A machine built of up to 5 Microchip
MPF300-SPLASH-KITS:https://www.microchipdirect.com/dev-tools/MPF300-SPLASH-KIT?exact=true&allDevTools=true
These cards have several capabilities but of most interest is probably 1G
Ethernet, 1 GB DDR4, and a (x4) 12 Gbps transceiver interface (PCIe edge
connection at the bottom of the card). The Host connection would be Ethernet.
The transceivers would be the card interconnect via a simple backplane. The
four transceivers would provide a completely connected graph for five nodes so
that each each card/fpga would have direct access to up to four neighbors, a
virtual FPGA 4 times as large. One of the interesting features of this FPGA is
that the internal PCIe protocol block is Gen2 (5 Gbps), but the transceivers
are 12 Gbps. Implementing point to point raw SERDES not only raises the speed
limit but eliminates the need for an external PCIe switch on the backplane. :-)
This machine is clearly not optimized, but I want to focus on architecture and
IP rather than investing a large amount of upfront time in Altium and
fabrication tasks.
Now the hard part, Application Ideas???
Kevin Schilf
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