Author: jaguarondi
Date: 2008-07-09 15:49:53 +0200 (Wed, 09 Jul 2008)
New Revision: 1318
Modified:
firmware/rf/trunk/defines.h
firmware/rf/trunk/rf_ctrl.c
Log:
* I didn't changed the timings yet but started to redefine them all.
Modified: firmware/rf/trunk/defines.h
===================================================================
--- firmware/rf/trunk/defines.h 2008-07-09 09:47:18 UTC (rev 1317)
+++ firmware/rf/trunk/defines.h 2008-07-09 13:49:53 UTC (rev 1318)
@@ -98,22 +98,68 @@
/* S[SC] of channel 0 in RX mode, p. 10 of datasheet */
#define CH00RX 28
+#define POLL_LOOPS 4
+
/*
* T_SLOT == 1ms ==> every 1000us 48 Bytes of payload are exchanged
+ * 1 tick = 578,704ns
*/
-#define POLL_LOOPS 4
-#define T_1ms 1728 //exact -> 1000us
-#define T_PWR_UP_TX 69 //69 == 40us(39.93)
-#define T_LOOP_TX 363 //363 == 210us(210.07)
-#define T_TX2RX 1296 //1296 == 750us(749.99)
-#define T_PWR_UP_RX 69 //69 == 40us(39.93)
-#define T_LOOP_RX 276 //276 == 160us(159.72)
-#define T_RX_ON 87 //87 == 50us(50.35)
-#define T_MAX_PAC_RX 1124 //1124 == 650us(650.46)
-#define T_RX2TX 172 //172 == 100us(99.54)
-#define T_TS_SOLL 979 //979 == 566.32us(566.55)
-#define T_START_SYNC 1086//1065 - 31 //(1065 - 31) == 616.32us(616.09) [31 ==
calc time!!(17.94us)]
-#define T_SYNC 1086//1065 //1065 == 616.32(616.32)
+#define T_1ms 1728 /* Exactly -> 1000us */
+
+#define PREAMBLE 8 /* Preamble in bytes */
+#define SYNC 2 /* Sync data in bytes */
+#define SOF 4 /* Start Of Frame in bytes */
+#define PAYLOAD 48 /* Payload in bytes */
+
+/* USART bit to tick ratio: sys_clk / (8 * 1152e3) */
+#define TICKS_PER_BIT (F_CPU/(8.*1152000))
+/* USART bits per byte
+ * (8bits + start + stop) */
+#define BITS_PER_BYTE 10
+/* HEADER duration */
+#define T_HEADER ((PREAMBLE + SYNC + SOF) * BITS_PER_BYTE * TICKS_PER_BIT) //
210
+/* PAYLOAD duration */
+#define T_PAYLOAD (PAYLOAD * BITS_PER_BYTE * TICKS_PER_BIT) // 720
+
+/* Power-up (> 40us) */
+#define T_PWR_UP 69 /* 40us */
+/* Programming (~20us) and PLL loop (>200us) */
+#define T_LOOP_TX 363 /* 210us */ /*XXX should be 220us */
+#define T_TX2RX 1296 /* 750us */
+/* RX on (>50us) before active RX-slot */
+#define T_RX_ON 87 /* 50us */
+/* Programming (~30us) and PLL loop (>200us) but next IRQ is at RX_ON */
+#define T_LOOP_RX (T_LOOP_TX - T_RX_ON)
+
+#define T_MAX_PAC_RX 1124 /* 650us */
+#define T_RX2TX (2*T_1ms - T_PWR_UP - T_LOOP_TX - T_TX2RX - T_PWR_UP - \
+ T_LOOP_RX - T_RX_ON - T_MAX_PAC_RX) /* Remaining up to 2ms
*/// 172
+
+#define T_START_SYNC 1086
+
+/* 2->3 (T_TX2RX) should be equal to 6->0
+ * 6->0 is (T_MAX_PAC_RX + T_RX2TX) for master
+ * ts->0 is (-T_HEADER + T_MAX_PAC_RX + T_RX2TX) for slave */
+#define T_SYNC 1086
// ==> 48KB/second (384.000bps)
+//#define T_1ms 1728 [> Exactly -> 1000us <]
+//#define T_PWR_UP_TX 69 [> 40us <]
+//#define T_LOOP_TX 363 [> 210us <]
+//#define T_TX2RX 1296 [> 750us <]
+//#define T_PWR_UP_RX 69 [> 40us <]
+//#define T_LOOP_RX 276 [> 160us <]
+//#define T_RX_ON 87 [> 50us <]
+//#define T_MAX_PAC_RX 1124 [> 650us <]
+//#define T_RX2TX (2*T_1ms - T_PWR_UP_TX - T_LOOP_TX - T_TX2RX - T_PWR_UP_RX -
+ //T_LOOP_RX - T_RX_ON - T_MAX_PAC_RX) [> Remaining up to 2ms
<]
+
+//#define T_START_SYNC 1086
+
+/* 2->3 (T_TX2RX) should be equal to 6->0
+ * 6->0 is (T_MAX_PAC_RX + T_RX2TX) for master
+ * 6->0 is (ts - T_PREAMBLE + T_MAX_PAC_RX + T_RX2TX) for slave */
+//#define T_SYNC 1086
+//// ==> 48KB/second (384.000bps)
+
#endif /* DEFINES_H */
Modified: firmware/rf/trunk/rf_ctrl.c
===================================================================
--- firmware/rf/trunk/rf_ctrl.c 2008-07-09 09:47:18 UTC (rev 1317)
+++ firmware/rf/trunk/rf_ctrl.c 2008-07-09 13:49:53 UTC (rev 1318)
@@ -48,6 +48,7 @@
ISR (SIG_OUTPUT_COMPARE1A)
{
+ PORTD ^= 0x08; // XXX DEBUG
switch(rf_state)
{
/*
@@ -56,7 +57,7 @@
case 0x00:
/* Power up for TX. */
pwr_up_atr2406();
- OCR1A = OCR1A+T_PWR_UP_TX;
+ OCR1A = OCR1A + T_PWR_UP;
break;
case 0x01:
/* Configure in TX. */
@@ -136,7 +137,7 @@
}
pwr_up_atr2406();
- OCR1A = OCR1A+T_PWR_UP_RX;
+ OCR1A = OCR1A + T_PWR_UP;
break;
case 0x04:
/* Configure in RX mode. */
@@ -200,7 +201,7 @@
if (rf_status & SLAVE)
/* SLAVE, resynchronize. */
{
- OCR1A = ts+T_SYNC-26;
+ OCR1A = ts + T_SYNC;
}
else
/* MASTER */
@@ -216,14 +217,17 @@
break;
}
rf_state = (rf_state + 1) & 7;
+ PORTD ^= 0x08; // XXX DEBUG
}
+volatile uint16_t testt = T_HEADER;
/*
* Setup 16 bit timer1 which is used to generate all RF related timings.
* We're using a crystal @ sys_clk = 13.824 MHz
*/
void start_rf_timer(void)
{
+ testt = T_RX2TX;
TCNT1H = 0x00;
TCNT1L = 0x00;
TCCR1A = 0x00;
@@ -456,6 +460,11 @@
//* Size: tbd *
//* Date: *
//*****************************************************************************
+/* There's a latency between the time the master sends the first byte of the
+ * pauload and the time the slave captures the last byte of the header. This
+ * value could be calculated by looking at the assembly or using an
+ * oscilloscope. */
+#define T_LATENCY 30
ISR(SIG_USART_RECV)
{
uint8_t data, state;
@@ -493,7 +502,7 @@
{
if(++state==0x04)
{
- ts = TCNT1;
+ ts = TCNT1 - T_LATENCY;
}
}
else
@@ -503,6 +512,7 @@
}
rf_rx_state = state;
}
+
//worsest case duration 70 cycles = but as this is the case only with the
//last byte it is no problem!!
//meaningfull worsest case is 54
-------------------------------------------------------------------------
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