Author: jaguarondi
Date: 2008-07-09 16:27:46 +0200 (Wed, 09 Jul 2008)
New Revision: 1319
Modified:
firmware/rf/trunk/defines.h
firmware/rf/trunk/prot.c
firmware/rf/trunk/rf_ctrl.c
Log:
* Some more re-arranging of the defines. I go step by step.
Modified: firmware/rf/trunk/defines.h
===================================================================
--- firmware/rf/trunk/defines.h 2008-07-09 13:49:53 UTC (rev 1318)
+++ firmware/rf/trunk/defines.h 2008-07-09 14:27:46 UTC (rev 1319)
@@ -124,25 +124,30 @@
/* Power-up (> 40us) */
#define T_PWR_UP 69 /* 40us */
/* Programming (~20us) and PLL loop (>200us) */
-#define T_LOOP_TX 363 /* 210us */ /*XXX should be 220us */
-#define T_TX2RX 1296 /* 750us */
+#define T_LOOP 363 /* 210us */ /*XXX should be 220us */
+/* Sending the HEAER and PAYLOAD */
+#define T_ACTIVE 1124 /* 650us */
+#define T_PWR_DWN (T_1ms - T_PWR_UP - T_LOOP - T_ACTIVE)
+
+#define T_TX2RX (T_ACTIVE + T_PWR_DWN)
+
/* RX on (>50us) before active RX-slot */
#define T_RX_ON 87 /* 50us */
/* Programming (~30us) and PLL loop (>200us) but next IRQ is at RX_ON */
-#define T_LOOP_RX (T_LOOP_TX - T_RX_ON)
+#define T_LOOP_RX (T_LOOP - T_RX_ON)
-#define T_MAX_PAC_RX 1124 /* 650us */
-#define T_RX2TX (2*T_1ms - T_PWR_UP - T_LOOP_TX - T_TX2RX - T_PWR_UP - \
- T_LOOP_RX - T_RX_ON - T_MAX_PAC_RX) /* Remaining up to 2ms
*/// 172
-
-#define T_START_SYNC 1086
-
/* 2->3 (T_TX2RX) should be equal to 6->0
* 6->0 is (T_MAX_PAC_RX + T_RX2TX) for master
* ts->0 is (-T_HEADER + T_MAX_PAC_RX + T_RX2TX) for slave */
#define T_SYNC 1086
// ==> 48KB/second (384.000bps)
+/* There's a latency between the time the master sends the first byte of the
+ * pauload and the time the slave captures the last byte of the header. This
+ * value could be calculated by looking at the assembly or using an
+ * oscilloscope. */
+#define T_LATENCY 26
+
//#define T_1ms 1728 [> Exactly -> 1000us <]
//#define T_PWR_UP_TX 69 [> 40us <]
//#define T_LOOP_TX 363 [> 210us <]
Modified: firmware/rf/trunk/prot.c
===================================================================
--- firmware/rf/trunk/prot.c 2008-07-09 13:49:53 UTC (rev 1318)
+++ firmware/rf/trunk/prot.c 2008-07-09 14:27:46 UTC (rev 1319)
@@ -127,7 +127,7 @@
j = j - ts;
/* Changing prescaler!! */
j = j << 3;
- OCR1A = T_START_SYNC - j;
+ OCR1A = T_SYNC - j;
start_rf_timer();
return;
Modified: firmware/rf/trunk/rf_ctrl.c
===================================================================
--- firmware/rf/trunk/rf_ctrl.c 2008-07-09 13:49:53 UTC (rev 1318)
+++ firmware/rf/trunk/rf_ctrl.c 2008-07-09 14:27:46 UTC (rev 1319)
@@ -81,7 +81,7 @@
init_atr2406(channel,TXEN);//configure ATR2406 to desired channel
UCSR0A = 0x40;
UCSR0B = 0x08;
- OCR1A = OCR1A+T_LOOP_TX;
+ OCR1A = OCR1A + T_LOOP;
//calculate new RF-Packet! SOF depending wether connected or not!!
rf_buffer_tx[8] = channel;
@@ -179,7 +179,7 @@
UCSR0A = 0x00;
UCSR0B = 0x90;
UCSR0C = 0x46;
- OCR1A = OCR1A+T_MAX_PAC_RX;
+ OCR1A = OCR1A + T_ACTIVE;
break;
case 0x07:
/* RX complete, check what we got. */
@@ -201,18 +201,18 @@
if (rf_status & SLAVE)
/* SLAVE, resynchronize. */
{
- OCR1A = ts + T_SYNC;
+ OCR1A = ts + T_SYNC - T_LATENCY;
}
else
/* MASTER */
{
- OCR1A = OCR1A+T_RX2TX;
+ OCR1A = OCR1A + T_PWR_DWN;
}
}
else
/* Wrong frame, just continue. */
{
- OCR1A = OCR1A+T_RX2TX;
+ OCR1A = OCR1A + T_PWR_DWN;
}
break;
}
@@ -227,7 +227,6 @@
*/
void start_rf_timer(void)
{
- testt = T_RX2TX;
TCNT1H = 0x00;
TCNT1L = 0x00;
TCCR1A = 0x00;
@@ -460,11 +459,6 @@
//* Size: tbd *
//* Date: *
//*****************************************************************************
-/* There's a latency between the time the master sends the first byte of the
- * pauload and the time the slave captures the last byte of the header. This
- * value could be calculated by looking at the assembly or using an
- * oscilloscope. */
-#define T_LATENCY 30
ISR(SIG_USART_RECV)
{
uint8_t data, state;
@@ -502,7 +496,7 @@
{
if(++state==0x04)
{
- ts = TCNT1 - T_LATENCY;
+ ts = TCNT1;
}
}
else
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