Author: jaguarondi
Date: 2008-07-10 13:10:13 +0200 (Thu, 10 Jul 2008)
New Revision: 1320
Modified:
firmware/rf/trunk/defines.h
firmware/rf/trunk/prot.c
firmware/rf/trunk/rf_ctrl.c
firmware/rf/trunk/varis.h
Log:
* Changed the timing so that I should now be able to have a payload of 75 byes.
Modified: firmware/rf/trunk/defines.h
===================================================================
--- firmware/rf/trunk/defines.h 2008-07-09 14:27:46 UTC (rev 1319)
+++ firmware/rf/trunk/defines.h 2008-07-10 11:10:13 UTC (rev 1320)
@@ -109,7 +109,7 @@
#define PREAMBLE 8 /* Preamble in bytes */
#define SYNC 2 /* Sync data in bytes */
#define SOF 4 /* Start Of Frame in bytes */
-#define PAYLOAD 48 /* Payload in bytes */
+#define PAYLOAD 75 /* Payload in bytes */
/* USART bit to tick ratio: sys_clk / (8 * 1152e3) */
#define TICKS_PER_BIT (F_CPU/(8.*1152000))
@@ -117,16 +117,18 @@
* (8bits + start + stop) */
#define BITS_PER_BYTE 10
/* HEADER duration */
-#define T_HEADER ((PREAMBLE + SYNC + SOF) * BITS_PER_BYTE * TICKS_PER_BIT) //
210
+#define T_HEADER (uint16_t)((PREAMBLE + SYNC + SOF) * BITS_PER_BYTE *
TICKS_PER_BIT) // 210
/* PAYLOAD duration */
-#define T_PAYLOAD (PAYLOAD * BITS_PER_BYTE * TICKS_PER_BIT) // 720
+#define T_PAYLOAD (uint16_t)(PAYLOAD * BITS_PER_BYTE * TICKS_PER_BIT) // 720
/* Power-up (> 40us) */
-#define T_PWR_UP 69 /* 40us */
+#define T_PWR_UP 0//69 /* 40us */
/* Programming (~20us) and PLL loop (>200us) */
-#define T_LOOP 363 /* 210us */ /*XXX should be 220us */
+#define T_LOOP 380
/* Sending the HEAER and PAYLOAD */
-#define T_ACTIVE 1124 /* 650us */
+//#define T_ACTIVE 1124 /* 650us */
+#define T_MARGIN 20
+#define T_ACTIVE (T_HEADER + T_PAYLOAD + T_MARGIN)
#define T_PWR_DWN (T_1ms - T_PWR_UP - T_LOOP - T_ACTIVE)
#define T_TX2RX (T_ACTIVE + T_PWR_DWN)
@@ -137,16 +139,16 @@
#define T_LOOP_RX (T_LOOP - T_RX_ON)
/* 2->3 (T_TX2RX) should be equal to 6->0
- * 6->0 is (T_MAX_PAC_RX + T_RX2TX) for master
- * ts->0 is (-T_HEADER + T_MAX_PAC_RX + T_RX2TX) for slave */
-#define T_SYNC 1086
+ * 6->0 is (T_MAX_PAC_RX + T_PWR_DWN) for master
+ * ts->0 is (-T_HEADER + T_ACTIVE + T_PWR_DWN) for slave */
+#define T_SYNC (-T_HEADER + T_ACTIVE + T_PWR_DWN)
// ==> 48KB/second (384.000bps)
/* There's a latency between the time the master sends the first byte of the
- * pauload and the time the slave captures the last byte of the header. This
- * value could be calculated by looking at the assembly or using an
- * oscilloscope. */
-#define T_LATENCY 26
+ * payload and the time the slave captures the last byte of the header. This
+ * value is better checked with an oscilloscope: the first byte of the preamble
+ * should be received 50us (T_RX_ON) after RX_ON is set. */
+#define T_LATENCY 10
//#define T_1ms 1728 [> Exactly -> 1000us <]
//#define T_PWR_UP_TX 69 [> 40us <]
Modified: firmware/rf/trunk/prot.c
===================================================================
--- firmware/rf/trunk/prot.c 2008-07-09 14:27:46 UTC (rev 1319)
+++ firmware/rf/trunk/prot.c 2008-07-10 11:10:13 UTC (rev 1320)
@@ -118,12 +118,13 @@
if(rf_rx_state==0xFF){//something received
if(checksum==0x00){//correct received
if(rf_buffer_rx[0]==52){//packet received
- pwr_dwn_atr2406();
+ //pwr_dwn_atr2406();
rf_rx_state = 0x00;
rf_status |= SLAVE;
j = TCNT1;
+ /* XXX have to change this so ts isn't global
anymore */
j = j - ts;
/* Changing prescaler!! */
j = j << 3;
@@ -142,6 +143,7 @@
/* MASTER mode. */
rf_status |= MASTER;
pwr_dwn_atr2406();
+ pwr_up_atr2406();
start_rf_timer();
UCSR0A = 0x00;
UCSR0B = 0x00;
Modified: firmware/rf/trunk/rf_ctrl.c
===================================================================
--- firmware/rf/trunk/rf_ctrl.c 2008-07-09 14:27:46 UTC (rev 1319)
+++ firmware/rf/trunk/rf_ctrl.c 2008-07-10 11:10:13 UTC (rev 1320)
@@ -30,6 +30,8 @@
volatile int8_t spi_tmp; /* XXX debug */
uint8_t checksum_tx;
+static void reset_atr2406(void);
+
//*****************************************************************************
//* Project: RF-Firmware for ISM *
//* Function: TIM1_COMPA_IRQ *
@@ -56,10 +58,31 @@
*/
case 0x00:
/* Power up for TX. */
- pwr_up_atr2406();
- OCR1A = OCR1A + T_PWR_UP;
- break;
+ //OCR1A = OCR1A + T_PWR_UP;
+ //pwr_up_atr2406();
+ //break;
+ rf_state = 1;
case 0x01:
+ /* RX complete, check what we got. */
+ UCSR0A = 0x00;
+ UCSR0B = 0x00;
+ UCSR0C = 0x00;
+ reset_atr2406();
+
+ /* XXX thought we shouldn't power down at full rate */
+ //pwr_dwn_atr2406();
+
+ if (rf_rx_state==0xFF)
+ /* Good frame received. */
+ {
+ if (checksum==0x00)
+ {
+ /* Switch rx buffer */
+ uint8_t volatile *p = rf_buffer_rx;
+ rf_buffer_rx = rf_buffer_rx_full;
+ rf_buffer_rx_full = p;
+ }
+ }
/* Configure in TX. */
#ifdef NOHOPP
channel = TRX_CHANNEL;
@@ -120,6 +143,7 @@
* case it's possible to extend slightly the com period. */
spi_tmp = spi_complete();
+ rf_state = 3; // XXX skip PU
break;
/*
@@ -127,6 +151,7 @@
*/
case 0x03:
/* End of TX, power up for RX. */
+ OCR1A = OCR1A + T_PWR_UP;
/* Request a SPI communication. */
/* XXX Should check here whether we're connected or not */
@@ -136,11 +161,12 @@
spi_request();
}
- pwr_up_atr2406();
- OCR1A = OCR1A + T_PWR_UP;
+ //pwr_up_atr2406();
break;
case 0x04:
/* Configure in RX mode. */
+ reset_atr2406();
+ spi_request();
#ifdef NOHOPP
channel = TRX_CHANNEL;
#endif
@@ -179,29 +205,34 @@
UCSR0A = 0x00;
UCSR0B = 0x90;
UCSR0C = 0x46;
- OCR1A = OCR1A + T_ACTIVE;
+ OCR1A = OCR1A + T_ACTIVE + T_PWR_DWN;
+ rf_state = 0; // XXX skip PU
break;
case 0x07:
/* RX complete, check what we got. */
UCSR0A = 0x00;
UCSR0B = 0x00;
UCSR0C = 0x00;
+ reset_atr2406();
/* XXX thought we shouldn't power down at full rate */
//pwr_dwn_atr2406();
- if ((rf_rx_state==0xFF) && (checksum==0x00))
+ if (rf_rx_state==0xFF)
/* Good frame received. */
{
- /* Switch rx buffer */
- uint8_t volatile *p = rf_buffer_rx;
- rf_buffer_rx = rf_buffer_rx_full;
- rf_buffer_rx_full = p;
+ if (checksum==0x00)
+ {
+ /* Switch rx buffer */
+ uint8_t volatile *p = rf_buffer_rx;
+ rf_buffer_rx = rf_buffer_rx_full;
+ rf_buffer_rx_full = p;
+ }
if (rf_status & SLAVE)
- /* SLAVE, resynchronize. */
+ /* SLAVE, resynchronized already. */
{
- OCR1A = ts + T_SYNC - T_LATENCY;
+ //OCR1A = ts + T_SYNC - T_LATENCY;
}
else
/* MASTER */
@@ -214,6 +245,7 @@
{
OCR1A = OCR1A + T_PWR_DWN;
}
+ rf_state = 0; // XXX skip PU
break;
}
rf_state = (rf_state + 1) & 7;
@@ -227,6 +259,7 @@
*/
void start_rf_timer(void)
{
+ testt = T_PWR_DWN;
TCNT1H = 0x00;
TCNT1L = 0x00;
TCCR1A = 0x00;
@@ -353,6 +386,17 @@
DDRD = DDRD|0x10;//XCK PIN set to output!!
}
+void reset_atr2406(void)
+{
+ set_nole(); //close loop
+ set_enable();
+ clr_rxon(); //switch off RX
+ clr_txon(); //switch off TX
+ clr_clock();
+ clr_data();
+ DDRD = DDRD|0x10;//XCK PIN set to output!!
+}
+
//*****************************************************************************
//* Project: RF-Firmware for ISM *
//* Function: pwr_dwn_atr2406 *
@@ -436,7 +480,7 @@
UCSR0A = 0x00;
UCSR0B = 0x00;
UCSR0C = 0x00;
- clr_pupwr();
+ //clr_pupwr();
clr_txon();
clr_enable();
set_nole();
@@ -485,7 +529,7 @@
UCSR0A = 0x00;
UCSR0B = 0x00;
UCSR0C = 0x00;
- clr_pupwr();
+ //clr_pupwr();
clr_rxon();
}
}
@@ -496,7 +540,10 @@
{
if(++state==0x04)
{
+#ifdef _SLAVE
ts = TCNT1;
+ OCR1A = ts + T_SYNC - T_LATENCY - T_PWR_DWN;
+#endif
}
}
else
Modified: firmware/rf/trunk/varis.h
===================================================================
--- firmware/rf/trunk/varis.h 2008-07-09 14:27:46 UTC (rev 1319)
+++ firmware/rf/trunk/varis.h 2008-07-10 11:10:13 UTC (rev 1320)
@@ -46,29 +46,17 @@
#include "defines.h"
-uint8_t GFCS;
+extern uint8_t GFCS;
extern volatile uint8_t rf_buffer_tx[];
extern uint8_t volatile *rf_buffer_rx;
extern uint8_t volatile *rf_buffer_rx_full;
-
extern uint8_t sof_ary[];
-
-
-
extern volatile uint8_t rf_status;
extern volatile uint8_t channel;
extern uint8_t channel_width;
-
-
-
extern volatile uint8_t tx_pac_len;
-
-
-
extern volatile uint8_t protocol_flags;
-
-
extern volatile uint8_t rf_tx_counter;
extern volatile uint8_t rf_rx_counter;
extern volatile uint8_t rf_rx_state;
@@ -76,8 +64,4 @@
extern volatile uint8_t trial_cnt;
extern volatile uint16_t ts;
-
-
-
-
#endif
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