From: Stephen Boyd <swb...@chromium.org> Enable the serial engine clk in probe so that this driver can work on platforms that don't already initialize the clk for this device before this driver runs. This fixes a problem I see on Coreboot platforms like Trogdor where the UART hardware isn't enabled by coreboot unless the serial console build is used.
Signed-off-by: Stephen Boyd <swb...@chromium.org> --- drivers/serial/serial_msm_geni.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 44603ead77cd9f7948a2bf52ebddfebbfeb9f1c2..35e0029144be7948eb5ab0da5a2d1317a08fb0c5 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -130,8 +130,9 @@ DECLARE_GLOBAL_DATA_PTR; struct msm_serial_data { phys_addr_t base; u32 baud; u32 oversampling; + struct clk *se; }; unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 32000000, 48000000, 64000000, 80000000, @@ -180,21 +181,8 @@ static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div) *clk_div = ser_clk / desired_clk; return ser_clk; } -static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate) -{ - struct clk *clk; - int ret; - - clk = devm_clk_get(dev, NULL); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - ret = clk_set_rate(clk, rate); - return ret; -} - /** * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine * @base: Pointer to the concerned serial engine. * @@ -251,9 +239,9 @@ static int msm_serial_setbrg(struct udevice *dev, int baud) priv->baud = baud; clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); - ret = geni_serial_set_clock_rate(dev, clk_rate); + ret = clk_set_rate(priv->se, clk_rate); if (ret < 0) { pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); return ret; } @@ -560,8 +548,18 @@ static inline void geni_serial_init(struct udevice *dev) static int msm_serial_probe(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); int ret; + struct clk *clk; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + priv->se = clk; + + ret = clk_enable(clk); + if (ret) + return ret; ret = geni_set_oversampling(dev); if (ret < 0) return ret; -- 2.50.0