On Tue, Jul 29, 2025 at 04:24:17PM +0000, Uros Stajic wrote: > From: Chao-ying Fu <c...@mips.com> > > This patch adds software emulation for atomic memory operations (AMO) > instructions that may not be supported in hardware. > > The `emu-amo.s` file provides assembly implementations of the > aforementioned operations. Corresponding handler logic is integrated > into the illegal instruction trap to catch and emulate unsupported > AMO* instructions at runtime.
The main body of U-Boot is executed by only one CPU, so I don't think there're chances for atomic instructions; disassembly of a U-Boot binary built with qemu-riscv64_smode_defconfig confirms the idea: the only four amo instructions locate in arch/riscv/cpu/start.S for picking the HART to run U-Boot. I suggest implementing a LR/SC-based codepath for HART lottery logic in start.S, and introducing a new Kconfig entry (maybe CONFIG_ISA_ZAMMO) to represent the availability of Zammo extension. We could use the alternative path for RISC-V platforms that don't implement Zammo and disable CONFIG_ISA_ZAAMO, which saves a lot of lines and make the code cleaner. Regards, Yao Zi > Signed-off-by: Chao-ying Fu <c...@mips.com> > Signed-off-by: Uros Stajic <uros.sta...@htecgroup.com> > --- > arch/riscv/cpu/p8700/Makefile | 1 + > arch/riscv/cpu/p8700/emu-amo.S | 254 ++++++++++++++++++++++++++++ > arch/riscv/lib/interrupts.c | 299 +++++++++++++++++++++++++++++++++ > include/interrupt.h | 19 +++ > 4 files changed, 573 insertions(+) > create mode 100644 arch/riscv/cpu/p8700/emu-amo.S
