From: Dinesh Maniyam <dinesh.mani...@altera.com>
The existing 'bridge' command help was incomplete and contained a
spelling error. This patch updates the help text to clearly describe
the available bridge bit positions and their corresponding masks:
bit0: h2f/s2f
bit1: lwhps2fpga
bit2: f2h/f2s
On Stratix 10 devices, additional bridges are supported:
bit3: f2sdram0
bit4: f2sdram1
bit5: f2sdram2
The updated help also includes more descriptive command messages and
examples, making it easier for users to enable or disable bridges from
U-Boot.
Example:
bridge enable 0x3 # Enable h2f/s2f and lwhps2fpga
bridge disable 0x1 # Disable only h2f/s2f
Signed-off-by: Dinesh Maniyam <dinesh.mani...@altera.com>
---
arch/arm/mach-socfpga/misc.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 76747c2196a..1d709065fa7 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -223,8 +223,16 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int
argc,
U_BOOT_CMD(bridge, 3, 1, do_bridge,
"SoCFPGA HPS FPGA bridge control",
- "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1),
FPGA-to-HPS (Bit 2) bridges\n"
- "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA
(Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
+ "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1),
FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5)
bridges\n"
+ "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA
(Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit
5) bridges\n"
+ "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n"
+ "For example:\n"
+ "1) To enable and disable all bridges (command without mask):\n"
+ " a) bridge enable\n"
+ " b) bridge disable\n"
+ "2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges
(command with mask):\n"
+ " a) bridge enable 0x3\n"
+ " b) bridge disable 0x3\n"
""
);
--
2.35.3
