Hi, > -----Original Message----- > From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapa...@altera.com> > Sent: Friday, August 8, 2025 6:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt > <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong > <tien.fong.c...@altera.com>; Tom Rini <tr...@konsulko.com>; Ravulapalli, > Naresh Kumar <naresh.kumar.ravulapa...@altera.com> > Subject: [PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager > registers > > For successful reset staggering pulse operation, reset pulse override bit is > set. > Port overcurrent bit 1, which in reality reflects PIPE power present signal is > set to avoid giving false information of Vbus status to HPS controller. > > Signed-off-by: Naresh Kumar Ravulapalli > <nareshkumar.ravulapa...@altera.com> > --- > .../include/mach/system_manager_soc64.h | 12 +++++++++ > arch/arm/mach-socfpga/system_manager_soc64.c | 26 > ++++++++++++++++++- > 2 files changed, 37 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > index c2ca0a50e35..8a7d47bee44 100644 > --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void); > #define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 > #define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C > #define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 > +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0 0x1F0 > #define SYSMGR_SOC64_MPFE_CONFIG 0x228 > #define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 > #define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C > @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void); > #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK > BIT(0) > #define > ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_ > MASK BIT(0) > #define > ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) > + > +/* > + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0 > + * Bits[14:13] Port Overcurrent > + * Bit[12] Reset Pulse Override > + */ > +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR > GENMASK(14, 13) > +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR BIT(12) > +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR 1 > +// BIT 1 actually reflects PIPE power present signal
Using /* ... */ [...] Best regards, Tien Fong
