Hi Timur,
Just some nit-picking...
Timur Tabi wrote:
> The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
> and other boards. A small firwmare must be uploaded to its on-board memory
> before it can be enabled. This patch adds the code which uploads firmware
> (but not the firmware itself) and updates the MPC8349E-mITX, MPC8313E-RDB,
> and MPC837XE-RDB boards to use that code.
>
>
Is this switch able to pass traffic in a default configuration without
this firmware or is it dead?
<snip>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index b9723fa..5ae7cb7 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -57,6 +57,7 @@ COBJS-y += tigon3.o
> COBJS-y += tsec.o
> COBJS-y += tsi108_eth.o
> COBJS-y += uli526x.o
> +COBJS-y += vsc7385.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
> new file mode 100644
> index 0000000..39b077f
> --- /dev/null
> +++ b/drivers/net/vsc7385.c
>
I'm not 100% convinced that this is network code, but my opinion isn't
very strong and I can't really think of a better place (maybe
device/misc or device/non_free?)
> @@ -0,0 +1,100 @@
> +/*
> + * Vitesse 7385 Switch Firmware Upload
> + *
> + * Author: Timur Tabi <[EMAIL PROTECTED]>
> + *
> + * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
> + * under the terms of the GNU General Public License version 2. This
> + * program is licensed "as is" without any warranty of any kind, whether
> + * express or implied.
> + *
> + * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
> + * switch.
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +
>
I think Kim mentioned this will break some architectures. Just repeating it.
> +#ifdef CONFIG_VSC7385_ENET
> +
> +/*
> + * Upload a Vitesse VSC7385 firmware image to the hardware
> + *
> + * This function takes a pointer to a VSC7385 firmware image and a size, and
> + * uploads that firmware to the VSC7385.
> + *
> + * This firmware is typically located at a board-specific flash address,
> + * and the size is typically 8KB.
> + *
> + * The firmware is Vitesse proprietary.
> + *
> + * Further details on the register information can be obtained from Vitesse.
> + */
> +int vsc7385_upload_firmware(void *firmware, unsigned int size)
> +{
> + u8 *fw = firmware;
> +
> + u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
> + u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
> + u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
> + u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
> + u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
> + u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
> +
>
It looks to me that the data bus is 8 bits. Why are you defining
registers as 32 bits and using 32-bit accessors?
> + unsigned int i;
> + int ret = 0;
> +
> + out_be32(gloreset, 3);
> + udelay(200);
> +
> + out_be32(icpu_ctrl, 142);
>
When you write to the device, can you express the value in hex? It's
quicker for the reader (who has Vitesse datasheets, of course) to figure
out what you're doing.
> + udelay(20);
> +
> + out_be32(icpu_rom_map, 1);
> + udelay(20);
> +
> + /* Write the firmware to I-RAM */
> + out_be32(icpu_addr, 0);
> + udelay(20);
> +
> + for (i = 0; i < size; i++) {
> + out_be32(icpu_data, fw[i]);
> + udelay(20);
> + if (ctrlc())
> + return -EINTR;
> + }
> +
> + /* Read back and compare */
> + out_be32(icpu_addr, 0);
> + udelay(20);
> +
> + for (i = 0; i < size; i++) {
> + u8 value;
> +
> + value = (u8) in_be32(icpu_data);
> + udelay(20);
> + if (value != fw[i]) {
> + debug("VSC7385: Upload mismatch: address 0x%x, "
> + "read value 0x%x, image value 0x%x\n",
> + i, value, fw[i]);
> +
> + return -EIO;
> + }
> + if (ctrlc())
> + break;
> + }
> +
> + out_be32(icpu_ctrl, 11);
> + udelay(20);
> +
> +#ifdef DEBUG
> + printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
> + udelay(20);
> +#endif
> +
> + return 0;
> +}
> +
> +#endif
> diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
> index f12a3e6..9576fa5 100644
> --- a/include/configs/MPC8313ERDB.h
> +++ b/include/configs/MPC8313ERDB.h
> @@ -38,6 +38,14 @@
> #define CONFIG_PCI
> #define CONFIG_83XX_GENERIC_PCI
>
> +#define CONFIG_MISC_INIT_R
> +
> +/*
> + * On-board devices
> + */
> +#define CONFIG_VSC7385_ENET
> +
> +
> #ifdef CFG_66MHZ
> #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
> #elif defined(CFG_33MHZ)
> @@ -65,6 +73,22 @@
> #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
>
> /*
> + * Device configurations
> + */
> +
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE 0xFE7FE000
> +#define CONFIG_VSC7385_IMAGE_SIZE 8192
> +
> +#endif
> +
> +/*
> * DDR Setup
> */
> #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
> @@ -214,19 +238,24 @@
> #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
> #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
>
> +/* local bus read write buffer mapping */
> +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
>
Like here, bits 19-20 are 01, meaning an 8-bit port
> +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
> +#define CFG_LBLAWBAR3_PRELIM 0xFA000000
> +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
> +
> +/* Vitesse 7385 */
> +
> #define CFG_VSC7385_BASE 0xF0000000
>
> -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
> +#ifdef CONFIG_VSC7385_ENET
> +
> #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address
> */
> #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
> #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at
> VSC7385 base */
> #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
>
> -/* local bus read write buffer mapping */
> -#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
> -#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
> -#define CFG_LBLAWBAR3_PRELIM 0xFA000000
> -#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
> +#endif
>
> /* pass open firmware flat tree */
> #define CONFIG_OF_LIBFDT 1
> @@ -263,13 +292,6 @@
> #define CFG_I2C_OFFSET 0x3000
> #define CFG_I2C2_OFFSET 0x3100
>
> -/* TSEC */
> -#define CFG_TSEC1_OFFSET 0x24000
> -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
> -#define CFG_TSEC2_OFFSET 0x25000
> -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
> -#define CONFIG_NET_MULTI
> -
> /*
> * General PCI
> * Addresses are mapped 1-1.
> @@ -288,26 +310,31 @@
> #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
>
> /*
> - * TSEC configuration
> + * TSEC
> */
> #define CONFIG_TSEC_ENET /* TSEC ethernet support */
>
> -#ifndef CONFIG_NET_MULTI
> -#define CONFIG_NET_MULTI 1
> -#endif
> -
> -#define CONFIG_GMII 1 /* MII PHY management */
> -#define CONFIG_TSEC1 1
> +#define CONFIG_NET_MULTI
> +#define CONFIG_GMII /* MII PHY management */
>
> +#ifdef CONFIG_TSEC1
> +#define CONFIG_HAS_ETH0
> #define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_TSEC2 1
> +#define CFG_TSEC1_OFFSET 0x24000
> +#define TSEC1_PHY_ADDR 0x1c
> +#define TSEC1_FLAGS TSEC_GIGABIT
> +#define TSEC1_PHYIDX 0
> +#endif
> +
> +#ifdef CONFIG_TSEC2
> +#define CONFIG_HAS_ETH1
> #define CONFIG_TSEC2_NAME "TSEC1"
> -#define TSEC1_PHY_ADDR 0x1c
> -#define TSEC2_PHY_ADDR 4
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> +#define CFG_TSEC2_OFFSET 0x25000
> +#define TSEC2_PHY_ADDR 4
> +#define TSEC2_FLAGS TSEC_GIGABIT
> +#define TSEC2_PHYIDX 0
> +#endif
> +
>
> /* Options are: TSEC[0-1] */
> #define CONFIG_ETHPRIME "TSEC1"
> @@ -496,10 +523,13 @@
> */
> #define CONFIG_ENV_OVERWRITE
>
> +#ifdef CONFIG_HAS_ETH0
> #define CONFIG_ETHADDR 00:E0:0C:00:95:01
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_HAS_ETH0
> +#endif
> +
> +#ifdef CONFIG_HAS_ETH1
> #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
> +#endif
>
> #define CONFIG_IPADDR 10.0.0.2
> #define CONFIG_SERVERIP 10.0.0.1
> diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
> index 48c2736..0e50186 100644
> --- a/include/configs/MPC8349ITX.h
> +++ b/include/configs/MPC8349ITX.h
> @@ -68,12 +68,16 @@
>
> #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to
> here */
>
> +#define CONFIG_MISC_INIT_F
> +#define CONFIG_MISC_INIT_R
>
> -/* On-board devices */
> +/*
> + * On-board devices
> + */
>
> #ifdef CONFIG_MPC8349ITX
> #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the
> board */
> -#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
> +#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
> #endif
>
> #define CONFIG_PCI
> @@ -88,9 +92,6 @@
> /* I2C */
> #ifdef CONFIG_HARD_I2C
>
> -#define CONFIG_MISC_INIT_F
> -#define CONFIG_MISC_INIT_R
> -
> #define CONFIG_FSL_I2C
> #define CONFIG_I2C_MULTI_BUS
> #define CONFIG_I2C_CMD_TREE
> @@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message
> if we find only one. */
> #define CFG_FLASH_SIZE 16 /* FLASH size in MB */
> #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
>
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE 0xFEFFE000
> +#define CONFIG_VSC7385_IMAGE_SIZE 8192
> +
> +#endif
> +
> /*
> * BRx, ORx, LBLAWBARx, and LBLAWARx
> */
> @@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message
> if we find only one. */
>
> /* Vitesse 7385 */
>
> -#ifdef CONFIG_VSC7385
> -
> #define CFG_VSC7385_BASE 0xF8000000
>
> +#ifdef CONFIG_VSC7385_ENET
> +
> #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
>
Here you use mnemonics for describing the base register settings. I know
it's not new code, but it would be nice to be consistent
> #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT |
> OR_GPCM_XACS | \
> OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
> @@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message
> if we find only one. */
> #define CONFIG_HAS_ETH1
> #define CONFIG_TSEC2_NAME "TSEC1"
> #define CFG_TSEC2_OFFSET 0x25000
> -#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
> +
> #define TSEC2_PHY_ADDR 4
> #define TSEC2_PHYIDX 0
> #define TSEC2_FLAGS TSEC_GIGABIT
> @@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message
> if we find only one. */
> */
> #define CONFIG_ENV_OVERWRITE
>
> -#ifdef CONFIG_TSEC1
> +#ifdef CONFIG_HAS_ETH0
> #define CONFIG_ETHADDR 00:E0:0C:00:8C:01
> #endif
>
> -#ifdef CONFIG_TSEC2
> +#ifdef CONFIG_HAS_ETH1
> #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
> #endif
>
> diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
> index 2da4f29..066197f 100644
> --- a/include/configs/MPC837XERDB.h
> +++ b/include/configs/MPC837XERDB.h
> @@ -32,6 +32,14 @@
>
> #define CONFIG_PCI 1
>
> +#define CONFIG_MISC_INIT_R
> +
> +/*
> + * On-board devices
> + */
> +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
> +#define CONFIG_VSC7385_ENET
> +
> /*
> * System Clock Setup
> */
> @@ -118,6 +126,22 @@
> #define CFG_IMMR 0xE0000000
>
> /*
> + * Device configurations
> + */
> +
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE 0xFE7FE000
> +#define CONFIG_VSC7385_IMAGE_SIZE 8192
> +
> +#endif
> +
> +/*
> * DDR Setup
> */
> #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
> @@ -251,15 +275,19 @@
> #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
>
> +/* Vitesse 7385 */
> +
> #define CFG_VSC7385_BASE 0xF0000000
>
> -/* VSC7385 Gigabit Switch support */
> -#define CONFIG_VSC7385_ENET
> +#ifdef CONFIG_VSC7385_ENET
> +
> #define CFG_BR2_PRELIM 0xf0000801 /* Base address
> */
> #define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
> #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
> #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
>
> +#endif
> +
> /*
> * Serial Port
> */
> @@ -324,43 +352,43 @@
> #define CONFIG_NET_MULTI
> #define CONFIG_PCI_PNP /* do pci plug-and-play */
>
> -#undef CONFIG_EEPRO100
> #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> #endif /* CONFIG_PCI */
>
> -#ifndef CONFIG_NET_MULTI
> -#define CONFIG_NET_MULTI 1
> -#endif
> -
> /*
> * TSEC
> */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -#define CFG_TSEC1_OFFSET 0x24000
> -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
> -#define CFG_TSEC2_OFFSET 0x25000
> -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
> +#ifdef CONFIG_TSEC_ENET
>
> -/*
> - * TSEC ethernet configuration
> - */
> -#define CONFIG_GMII 1 /* MII PHY management */
> -#define CONFIG_TSEC1 1
> +#define CONFIG_NET_MULTI
> +#define CONFIG_GMII /* MII PHY management */
> +
> +#define CONFIG_TSEC1
> +
> +#ifdef CONFIG_TSEC1
> +#define CONFIG_HAS_ETH0
> #define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> +#define CFG_TSEC1_OFFSET 0x24000
> #define TSEC1_PHY_ADDR 2
> -#define TSEC2_PHY_ADDR 0x1c
> #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> #define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> +#endif
>
> +#ifdef CONFIG_TSEC2
> +#define CONFIG_HAS_ETH1
> +#define CONFIG_TSEC2_NAME "TSEC1"
> +#define CFG_TSEC2_OFFSET 0x25000
> +#define TSEC2_PHY_ADDR 0x1c
> +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> +#define TSEC2_PHYIDX 0
> +#endif
>
> /* Options are: TSEC[0-1] */
> #define CONFIG_ETHPRIME "TSEC0"
>
> +#endif
> +
> /*
> * Environment
> */
> @@ -529,10 +557,13 @@
> */
> #define CONFIG_ENV_OVERWRITE
>
> -#define CONFIG_HAS_ETH0 /* add support for
> "ethaddr" */
> -#define CONFIG_ETHADDR 00:04:9f:ef:04:01
> -#define CONFIG_HAS_ETH1 /* add support for
> "eth1addr" */
> -#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
> +#ifdef CONFIG_HAS_ETH0
> +#define CONFIG_ETHADDR 00:04:9f:ef:04:01
> +#endif
> +
> +#ifdef CONFIG_HAS_ETH1
> +#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
> +#endif
>
> #define CONFIG_IPADDR 10.0.0.2
> #define CONFIG_SERVERIP 10.0.0.1
> diff --git a/include/vsc7385.h b/include/vsc7385.h
> new file mode 100644
> index 0000000..0432499
> --- /dev/null
> +++ b/include/vsc7385.h
> @@ -0,0 +1,13 @@
> +/*
> + * Header file for vsc7385.c
> + *
> + * Author: Timur Tabi <[EMAIL PROTECTED]>
> + *
> + * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
> + * under the terms of the GNU General Public License version 2. This
> + * program is licensed "as is" without any warranty of any kind, whether
> + * express or implied.
> + */
> +
> +int vsc7385_upload_firmware(void *firmware, unsigned int size);
> +
>
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