Hello Stefan,
I had a look at all PPC440 processor manuals from AMCC and see that my
patch applies to all of them. In other words the #else portion is never
used. Therefore I am submitting a patch that cleans up this code quite
nicely.
Another observation that I made is that the PPC440EPx and PPC440GPx
require more than 32 bits to control the power management functions.
Therefore I defined a second set of registers cpc1_er, cpc1_fr, cpc1_sr
for these processors. These can be used as placeholders for future
development.
Let me know if this sounds good to you.
Regards,
Eugene
-----Original Message-----
From: Stefan Roese [mailto:[EMAIL PROTECTED]
Sent: April 4, 2008 10:05 AM
To: Eugene O'Brien
Subject: Re: Patch for PPC440EP
Hi Eugene,
On Friday 04 April 2008, Eugene O'Brien wrote:
> Here is patch for the PPC440EP. The DCR addresses of the power
> management registers were not correctly defined. This patch corrects
> that. You can check the PPC440EP UM p301 to confirm. I also used the
> BDI2000 to double check.
Thanks.
I suggest the following change:
Instead of:
-#if defined(CONFIG_440GX) || \
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
please use:
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
This way 440GP will be added too. And if we're at it, please check if
440EPx
and 440GRx also need this change. If yes, please include them too.
And please post the patch to the mailing list for review. I can't accept
patches without public review nowadays, since we changed the development
process.
Thanks for your input.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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=====================================================================
diff --git a/include/ppc440.h b/include/ppc440.h
index 80dd332..a4cf143 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1726,16 +1726,15 @@
#else
#define CNTRL_DCR_BASE 0x0b0
#endif
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register
*/
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register
*/
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register
*/
-#else
-#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register
*/
-#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register
*/
-#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register
*/
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define cpc1_er (CNTRL_DCR_BASE+0x40) /* CPM enable register
*/
+#define cpc1_fr (CNTRL_DCR_BASE+0x41) /* CPM force register
*/
+#define cpc1_sr (CNTRL_DCR_BASE+0x42) /* CPM status register
*/
#endif
#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0
*/
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