Dear John Rigby,
In message <[EMAIL PROTECTED]> you wrote:
> MPC5121 rev 2 silicon has a new register for controlling how long
> CS is asserted after deassertion of ALE in multiplexed mode.
>
> The default is to assert CS together with ALE. The alternative
> is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
>
> The default is wrong for the NOR flash and CPLD on the ADS5121.
>
> This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
> it does so conditionally based on silicon rev 2.0 or greater.
>
> Signed-off-by: Martha J Marx <[EMAIL PROTECTED]>
> Signed-off-by: John Rigby <[EMAIL PROTECTED]>
> ---
> board/ads5121/ads5121.c | 4 ++++
> include/configs/ads5121.h | 1 +
> include/mpc512x.h | 1 +
> 3 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
> index ba3d7d2..deaa292 100644
> --- a/board/ads5121/ads5121.c
> +++ b/board/ads5121/ads5121.c
> @@ -25,6 +25,7 @@
> #include <mpc512x.h>
> #include <asm/bitops.h>
> #include <command.h>
> +#include <asm/processor.h>
> #include <fdt_support.h>
> #ifdef CONFIG_MISC_INIT_R
> #include <i2c.h>
> @@ -92,6 +93,9 @@ int board_early_init_f (void)
> * Configure Flash Speed
> */
> *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
> + if (SVR_MJREV (im->sysconf.spridr) >= 2) {
> + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET +
> CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
> + }
We should stop using pointer accesses to registers and use the
appropriate accessor functions / macros instead (and probably even
convert oild, existing code before the next round of compiler
optimizations bites us).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
Premature optimization is the root of all evil. -- D.E. Knuth
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