Fabio Estevam wrote: > >> +#define NFC_BUF_ADDR (NFC_REG_BASE + 0x1E04) >> +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0x1E06) >> +#define NFC_FLASH_CMD (NFC_REG_BASE + 0x1E08) >> +#define NFC_CONFIG (NFC_REG_BASE + 0x1E0A) >> +#define NFC_ECC_STATUS1 (NFC_REG_BASE + 0x1E0C) >> +#define NFC_ECC_STATUS2 (NFC_REG_BASE + 0x1E0E) >> +#define NFC_SPAS (NFC_REG_BASE + 0x1E10) >> +#define NFC_WRPROT (NFC_REG_BASE + 0x1E12) >> +#define NFC_NF_WRPRST (NFC_REG_BASE + 0x1E18) >> +#define NFC_CONFIG1 (NFC_REG_BASE + 0x1E1A) >> +#define NFC_CONFIG2 (NFC_REG_BASE + 0x1E1C) >> +#define NFC_UNLOCKSTART_BLKADDR0 (NFC_REG_BASE + 0x1E20) >> +#define NFC_UNLOCKEND_BLKADDR0 (NFC_REG_BASE + 0x1E22) >> +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0x1E24) >> +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0x1E26) >> +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0x1E28) >> +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0x1E2A) >> +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0x1E2C) >> +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0x1E2E) >> > > On MX31 and also according to the current MPC5121 Reference Manual on the web > the offsets of the registers above seem to have an extra offset of 0x1000. > > MX31 and MPC5121 manuals state the following offsets: > > #define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04) > #define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06) > ... > > Is there a newer MPC5121 manual that changed the NAND registers offsets? > As the patch states this is for silicon rev2. One of the changes with rev2 was support for 4k nand so the number of 512 byte buffers is now 8 instead of 4 so everything else has moved up by 2K (0x1000).
The rev2 manual is available online here: http://www.freescale.com/files/32bit/doc/ref_manual/MPC5121ERM.pdf > Regards, > > Fabio Estevam > > > > > _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
