Hi Akshay, On Tue, Mar 5, 2013 at 5:19 AM, Akshay Saraswat <[email protected]> wrote: > SHA-256 and SHA-1 accelerated using ACE hardware. > > Tested with command "hash sha256 0x40008000 0x2B 0x40009000". > Used mm and md to write a standard string to memory location > 0x40008000 and ran the above command to verify the output. > > Signed-off-by: ARUN MANKUZHI <[email protected]> > Signed-off-by: Akshay Saraswat <[email protected]>
Just a nit below, probably a misunderstanding and my fault. Once that is fixed: Acked-by: Simon Glass <[email protected]> > --- > Changes since v1: > - Moved code to drivers/crypto. > - Fixed few other nits. > > Changes since v2: > - Added falling back to software sha256 in case length exceeds buffer > limit. > - Reduced one tab at lines 533, 559 and 571 in this patch. > - Removed space after a cast at line 506 in this patch. > - Removed blank line at line 561 in this patch. > - Removed space before semicolon at line 576 in this patch. > > Changes since v3: > - Removed buffer limit since there are 2 regs for address > hash_msg_size_high and low. > That means buffer length could go upto 2^64 bits which is > practically > - Removed falling back to software sha256 because there is no buffer > limit. > - Removed "/ 4" to sha1 and sha256 lengths and added increment to 4 > in for loop at line 573. > - Timed out still kept to be 100 ms since this is enough for hardware > to switch status to idle from busy. > In case it couldn't that means h/w is faulty. > > Makefile | 1 + > arch/arm/include/asm/arch-exynos/cpu.h | 4 + > drivers/crypto/Makefile | 47 +++++ > drivers/crypto/ace_sfr.h | 310 > +++++++++++++++++++++++++++++++++ > drivers/crypto/ace_sha.c | 122 +++++++++++++ > include/ace_sha.h | 42 +++++ > 6 files changed, 526 insertions(+) > create mode 100644 drivers/crypto/Makefile > create mode 100644 drivers/crypto/ace_sfr.h > create mode 100644 drivers/crypto/ace_sha.c > create mode 100644 include/ace_sha.h > > diff --git a/Makefile b/Makefile > index fc18dd4..4c41130 100644 > --- a/Makefile > +++ b/Makefile > @@ -272,6 +272,7 @@ LIBS-y += disk/libdisk.o > LIBS-y += drivers/bios_emulator/libatibiosemu.o > LIBS-y += drivers/block/libblock.o > LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o > +LIBS-y += drivers/crypto/libcrypto.o > LIBS-y += drivers/dma/libdma.o > LIBS-y += drivers/fpga/libfpga.o > LIBS-y += drivers/gpio/libgpio.o > diff --git a/arch/arm/include/asm/arch-exynos/cpu.h > b/arch/arm/include/asm/arch-exynos/cpu.h > index eb34422..2a20558 100644 > --- a/arch/arm/include/asm/arch-exynos/cpu.h > +++ b/arch/arm/include/asm/arch-exynos/cpu.h > @@ -62,6 +62,7 @@ > #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE > +#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE > > /* EXYNOS4X12 */ > #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 > @@ -95,6 +96,7 @@ > #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE > +#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE > > /* EXYNOS5 Common*/ > #define EXYNOS5_I2C_SPACING 0x10000 > @@ -106,6 +108,7 @@ > #define EXYNOS5_SWRESET 0x10040400 > #define EXYNOS5_SYSREG_BASE 0x10050000 > #define EXYNOS5_WATCHDOG_BASE 0x101D0000 > +#define EXYNOS5_ACE_SFR_BASE 0x10830000 > #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 > #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 > #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 > @@ -205,6 +208,7 @@ static inline unsigned int > samsung_get_base_##device(void) \ > > SAMSUNG_BASE(adc, ADC_BASE) > SAMSUNG_BASE(clock, CLOCK_BASE) > +SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) > SAMSUNG_BASE(dp, DP_BASE) > SAMSUNG_BASE(sysreg, SYSREG_BASE) > SAMSUNG_BASE(fimd, FIMD_BASE) > diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile > new file mode 100644 > index 0000000..2c54793 > --- /dev/null > +++ b/drivers/crypto/Makefile > @@ -0,0 +1,47 @@ > +# > +# Copyright (c) 2013 Samsung Electronics Co., Ltd. > +# http://www.samsung.com > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB := $(obj)libcrypto.o > + > +COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o > + > +COBJS := $(COBJS-y) > +SRCS := $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > + > +all: $(LIB) > + > +$(LIB): $(obj).depend $(OBJS) > + $(call cmd_link_o_target, $(OBJS)) > + > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################## > diff --git a/drivers/crypto/ace_sfr.h b/drivers/crypto/ace_sfr.h > new file mode 100644 > index 0000000..8f1c893 > --- /dev/null > +++ b/drivers/crypto/ace_sfr.h > @@ -0,0 +1,310 @@ > +/* > + * Header file for Advanced Crypto Engine - SFR definitions > + * > + * Copyright (c) 2012 Samsung Electronics > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + */ > + > +#ifndef __ACE_SFR_H > +#define __ACE_SFR_H > + > +struct exynos_ace_sfr { > + unsigned int fc_intstat; /* base + 0 */ > + unsigned int fc_intenset; > + unsigned int fc_intenclr; > + unsigned int fc_intpend; > + unsigned int fc_fifostat; > + unsigned int fc_fifoctrl; > + unsigned int fc_global; > + unsigned int res1; > + unsigned int fc_brdmas; > + unsigned int fc_brdmal; > + unsigned int fc_brdmac; > + unsigned int res2; > + unsigned int fc_btdmas; > + unsigned int fc_btdmal; > + unsigned int fc_btdmac; > + unsigned int res3; > + unsigned int fc_hrdmas; > + unsigned int fc_hrdmal; > + unsigned int fc_hrdmac; > + unsigned int res4; > + unsigned int fc_pkdmas; > + unsigned int fc_pkdmal; > + unsigned int fc_pkdmac; > + unsigned int fc_pkdmao; > + unsigned char res5[0x1a0]; > + > + unsigned int aes_control; /* base + 0x200 */ > + unsigned int aes_status; > + unsigned char res6[0x8]; > + unsigned int aes_in[4]; > + unsigned int aes_out[4]; > + unsigned int aes_iv[4]; > + unsigned int aes_cnt[4]; > + unsigned char res7[0x30]; > + unsigned int aes_key[8]; > + unsigned char res8[0x60]; > + > + unsigned int tdes_control; /* base + 0x300 */ > + unsigned int tdes_status; > + unsigned char res9[0x8]; > + unsigned int tdes_key[6]; > + unsigned int tdes_iv[2]; > + unsigned int tdes_in[2]; > + unsigned int tdes_out[2]; > + unsigned char res10[0xc0]; > + > + unsigned int hash_control; /* base + 0x400 */ > + unsigned int hash_control2; > + unsigned int hash_fifo_mode; > + unsigned int hash_byteswap; > + unsigned int hash_status; > + unsigned char res11[0xc]; > + unsigned int hash_msgsize_low; > + unsigned int hash_msgsize_high; > + unsigned int hash_prelen_low; > + unsigned int hash_prelen_high; > + unsigned int hash_in[16]; > + unsigned int hash_key_in[16]; > + unsigned int hash_iv[8]; > + unsigned char res12[0x30]; > + unsigned int hash_result[8]; > + unsigned char res13[0x20]; > + unsigned int hash_seed[8]; > + unsigned int hash_prng[8]; > + unsigned char res14[0x180]; > + > + unsigned int pka_sfr[5]; /* base + 0x700 */ > +}; > + > +/* ACE_FC_INT */ > +#define ACE_FC_PKDMA (1 << 0) > +#define ACE_FC_HRDMA (1 << 1) > +#define ACE_FC_BTDMA (1 << 2) > +#define ACE_FC_BRDMA (1 << 3) > +#define ACE_FC_PRNG_ERROR (1 << 4) > +#define ACE_FC_MSG_DONE (1 << 5) > +#define ACE_FC_PRNG_DONE (1 << 6) > +#define ACE_FC_PARTIAL_DONE (1 << 7) > + > +/* ACE_FC_FIFOSTAT */ > +#define ACE_FC_PKFIFO_EMPTY (1 << 0) > +#define ACE_FC_PKFIFO_FULL (1 << 1) > +#define ACE_FC_HRFIFO_EMPTY (1 << 2) > +#define ACE_FC_HRFIFO_FULL (1 << 3) > +#define ACE_FC_BTFIFO_EMPTY (1 << 4) > +#define ACE_FC_BTFIFO_FULL (1 << 5) > +#define ACE_FC_BRFIFO_EMPTY (1 << 6) > +#define ACE_FC_BRFIFO_FULL (1 << 7) > + > +/* ACE_FC_FIFOCTRL */ > +#define ACE_FC_SELHASH_MASK (3 << 0) > +#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source > */ > +#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */ > +#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output > */ > +#define ACE_FC_SELBC_MASK (1 << 2) > +#define ACE_FC_SELBC_AES (0 << 2) /* AES */ > +#define ACE_FC_SELBC_DES (1 << 2) /* DES */ > + > +/* ACE_FC_GLOBAL */ > +#define ACE_FC_SSS_RESET (1 << 0) > +#define ACE_FC_DMA_RESET (1 << 1) > +#define ACE_FC_AES_RESET (1 << 2) > +#define ACE_FC_DES_RESET (1 << 3) > +#define ACE_FC_HASH_RESET (1 << 4) > +#define ACE_FC_AXI_ENDIAN_MASK (3 << 6) > +#define ACE_FC_AXI_ENDIAN_LE (0 << 6) > +#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6) > +#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6) > + > +/* Feed control - BRDMA control */ > +#define ACE_FC_BRDMACFLUSH_OFF (0 << 0) > +#define ACE_FC_BRDMACFLUSH_ON (1 << 0) > +#define ACE_FC_BRDMACSWAP_ON (1 << 1) > +#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2) > +#define ACE_FC_BRDMACARPROT_OFS (2) > +#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5) > +#define ACE_FC_BRDMACARCACHE_OFS (5) > + > +/* Feed control - BTDMA control */ > +#define ACE_FC_BTDMACFLUSH_OFF (0 << 0) > +#define ACE_FC_BTDMACFLUSH_ON (1 << 0) > +#define ACE_FC_BTDMACSWAP_ON (1 << 1) > +#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2) > +#define ACE_FC_BTDMACAWPROT_OFS (2) > +#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5) > +#define ACE_FC_BTDMACAWCACHE_OFS (5) > + > +/* Feed control - HRDMA control */ > +#define ACE_FC_HRDMACFLUSH_OFF (0 << 0) > +#define ACE_FC_HRDMACFLUSH_ON (1 << 0) > +#define ACE_FC_HRDMACSWAP_ON (1 << 1) > +#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2) > +#define ACE_FC_HRDMACARPROT_OFS (2) > +#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5) > +#define ACE_FC_HRDMACARCACHE_OFS (5) > + > +/* Feed control - PKDMA control */ > +#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3) > +#define ACE_FC_PKDMACDESEND_ON (1 << 2) > +#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1) > +#define ACE_FC_PKDMACFLUSH_ON (1 << 0) > + > +/* Feed control - PKDMA offset */ > +#define ACE_FC_SRAMOFFSET_MASK (0xfff) > + > +/* AES control */ > +#define ACE_AES_MODE_MASK (1 << 0) > +#define ACE_AES_MODE_ENC (0 << 0) > +#define ACE_AES_MODE_DEC (1 << 0) > +#define ACE_AES_OPERMODE_MASK (3 << 1) > +#define ACE_AES_OPERMODE_ECB (0 << 1) > +#define ACE_AES_OPERMODE_CBC (1 << 1) > +#define ACE_AES_OPERMODE_CTR (2 << 1) > +#define ACE_AES_FIFO_MASK (1 << 3) > +#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */ > +#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode > */ > +#define ACE_AES_KEYSIZE_MASK (3 << 4) > +#define ACE_AES_KEYSIZE_128 (0 << 4) > +#define ACE_AES_KEYSIZE_192 (1 << 4) > +#define ACE_AES_KEYSIZE_256 (2 << 4) > +#define ACE_AES_KEYCNGMODE_MASK (1 << 6) > +#define ACE_AES_KEYCNGMODE_OFF (0 << 6) > +#define ACE_AES_KEYCNGMODE_ON (1 << 6) > +#define ACE_AES_SWAP_MASK (0x1f << 7) > +#define ACE_AES_SWAPKEY_OFF (0 << 7) > +#define ACE_AES_SWAPKEY_ON (1 << 7) > +#define ACE_AES_SWAPCNT_OFF (0 << 8) > +#define ACE_AES_SWAPCNT_ON (1 << 8) > +#define ACE_AES_SWAPIV_OFF (0 << 9) > +#define ACE_AES_SWAPIV_ON (1 << 9) > +#define ACE_AES_SWAPDO_OFF (0 << 10) > +#define ACE_AES_SWAPDO_ON (1 << 10) > +#define ACE_AES_SWAPDI_OFF (0 << 11) > +#define ACE_AES_SWAPDI_ON (1 << 11) > +#define ACE_AES_COUNTERSIZE_MASK (3 << 12) > +#define ACE_AES_COUNTERSIZE_128 (0 << 12) > +#define ACE_AES_COUNTERSIZE_64 (1 << 12) > +#define ACE_AES_COUNTERSIZE_32 (2 << 12) > +#define ACE_AES_COUNTERSIZE_16 (3 << 12) > + > +/* AES status */ > +#define ACE_AES_OUTRDY_MASK (1 << 0) > +#define ACE_AES_OUTRDY_OFF (0 << 0) > +#define ACE_AES_OUTRDY_ON (1 << 0) > +#define ACE_AES_INRDY_MASK (1 << 1) > +#define ACE_AES_INRDY_OFF (0 << 1) > +#define ACE_AES_INRDY_ON (1 << 1) > +#define ACE_AES_BUSY_MASK (1 << 2) > +#define ACE_AES_BUSY_OFF (0 << 2) > +#define ACE_AES_BUSY_ON (1 << 2) > + > +/* TDES control */ > +#define ACE_TDES_MODE_MASK (1 << 0) > +#define ACE_TDES_MODE_ENC (0 << 0) > +#define ACE_TDES_MODE_DEC (1 << 0) > +#define ACE_TDES_OPERMODE_MASK (1 << 1) > +#define ACE_TDES_OPERMODE_ECB (0 << 1) > +#define ACE_TDES_OPERMODE_CBC (1 << 1) > +#define ACE_TDES_SEL_MASK (3 << 3) > +#define ACE_TDES_SEL_DES (0 << 3) > +#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */ > +#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */ > +#define ACE_TDES_FIFO_MASK (1 << 5) > +#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */ > +#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */ > +#define ACE_TDES_SWAP_MASK (0xf << 6) > +#define ACE_TDES_SWAPKEY_OFF (0 << 6) > +#define ACE_TDES_SWAPKEY_ON (1 << 6) > +#define ACE_TDES_SWAPIV_OFF (0 << 7) > +#define ACE_TDES_SWAPIV_ON (1 << 7) > +#define ACE_TDES_SWAPDO_OFF (0 << 8) > +#define ACE_TDES_SWAPDO_ON (1 << 8) > +#define ACE_TDES_SWAPDI_OFF (0 << 9) > +#define ACE_TDES_SWAPDI_ON (1 << 9) > + > +/* TDES status */ > +#define ACE_TDES_OUTRDY_MASK (1 << 0) > +#define ACE_TDES_OUTRDY_OFF (0 << 0) > +#define ACE_TDES_OUTRDY_ON (1 << 0) > +#define ACE_TDES_INRDY_MASK (1 << 1) > +#define ACE_TDES_INRDY_OFF (0 << 1) > +#define ACE_TDES_INRDY_ON (1 << 1) > +#define ACE_TDES_BUSY_MASK (1 << 2) > +#define ACE_TDES_BUSY_OFF (0 << 2) > +#define ACE_TDES_BUSY_ON (1 << 2) > + > +/* Hash control */ > +#define ACE_HASH_ENGSEL_MASK (0xf << 0) > +#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0) > +#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0) > +#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0) > +#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0) > +#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0) > +#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0) > +#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0) > +#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0) > +#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0) > +#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0) > +#define ACE_HASH_ENGSEL_PRNG (0x8 << 0) > +#define ACE_HASH_STARTBIT_ON (1 << 4) > +#define ACE_HASH_USERIV_EN (1 << 5) > + > +/* Hash control 2 */ > +#define ACE_HASH_PAUSE_ON (1 << 0) > + > +/* Hash control - FIFO mode */ > +#define ACE_HASH_FIFO_MASK (1 << 0) > +#define ACE_HASH_FIFO_OFF (0 << 0) > +#define ACE_HASH_FIFO_ON (1 << 0) > + > +/* Hash control - byte swap */ > +#define ACE_HASH_SWAP_MASK (0xf << 0) > +#define ACE_HASH_SWAPKEY_OFF (0 << 0) > +#define ACE_HASH_SWAPKEY_ON (1 << 0) > +#define ACE_HASH_SWAPIV_OFF (0 << 1) > +#define ACE_HASH_SWAPIV_ON (1 << 1) > +#define ACE_HASH_SWAPDO_OFF (0 << 2) > +#define ACE_HASH_SWAPDO_ON (1 << 2) > +#define ACE_HASH_SWAPDI_OFF (0 << 3) > +#define ACE_HASH_SWAPDI_ON (1 << 3) > + > +/* Hash status */ > +#define ACE_HASH_BUFRDY_MASK (1 << 0) > +#define ACE_HASH_BUFRDY_OFF (0 << 0) > +#define ACE_HASH_BUFRDY_ON (1 << 0) > +#define ACE_HASH_SEEDSETTING_MASK (1 << 1) > +#define ACE_HASH_SEEDSETTING_OFF (0 << 1) > +#define ACE_HASH_SEEDSETTING_ON (1 << 1) > +#define ACE_HASH_PRNGBUSY_MASK (1 << 2) > +#define ACE_HASH_PRNGBUSY_OFF (0 << 2) > +#define ACE_HASH_PRNGBUSY_ON (1 << 2) > +#define ACE_HASH_PARTIALDONE_MASK (1 << 4) > +#define ACE_HASH_PARTIALDONE_OFF (0 << 4) > +#define ACE_HASH_PARTIALDONE_ON (1 << 4) > +#define ACE_HASH_PRNGDONE_MASK (1 << 5) > +#define ACE_HASH_PRNGDONE_OFF (0 << 5) > +#define ACE_HASH_PRNGDONE_ON (1 << 5) > +#define ACE_HASH_MSGDONE_MASK (1 << 6) > +#define ACE_HASH_MSGDONE_OFF (0 << 6) > +#define ACE_HASH_MSGDONE_ON (1 << 6) > +#define ACE_HASH_PRNGERROR_MASK (1 << 7) > +#define ACE_HASH_PRNGERROR_OFF (0 << 7) > +#define ACE_HASH_PRNGERROR_ON (1 << 7) > + > +#endif > diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c > new file mode 100644 > index 0000000..d33e405 > --- /dev/null > +++ b/drivers/crypto/ace_sha.c > @@ -0,0 +1,122 @@ > +/* > + * Advanced Crypto Engine - SHA Firmware > + * Copyright (c) 2012 Samsung Electronics > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + */ > +#include <common.h> > +#include <sha256.h> > +#include <sha1.h> > +#include <ace_sha.h> > +#include <asm/errno.h> > +#include "ace_sfr.h" > + > +/* > + * Timeout limit in case h/w fails. > + * operation should not spen more time than this. > + */ > +#define TIMEOUT_MS 100 > + > +/* SHA1 value for the message of zero length */ > +static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { > + 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D, > + 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90, > + 0xAF, 0xD8, 0x07, 0x09}; > + > +/* SHA256 value for the message of zero length */ > +static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = { > + 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14, > + 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24, > + 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, > + 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55}; > + > +int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len, > + unsigned char *pout, unsigned int hash_type) > +{ > + unsigned int i, reg, len; > + unsigned int *pdigest; > + ulong start; > + struct exynos_ace_sfr *ace_sha_reg = > + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); > + > + if (buf_len == 0) { > + /* ACE H/W cannot compute hash value for empty string */ > + if (hash_type == ACE_SHA_TYPE_SHA1) > + memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN); > + else > + memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN); > + return 0; > + } > + > + /* Flush HRDMA */ > + writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac); > + writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac); > + > + /* Set byte swap of data in */ > + writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON, > + &ace_sha_reg->hash_byteswap); > + > + /* Select Hash input mux as external source */ > + reg = readl(&ace_sha_reg->fc_fifoctrl); > + reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT; > + writel(reg, &ace_sha_reg->fc_fifoctrl); > + > + /* Set Hash as SHA1 or SHA256 and start Hash engine */ > + reg = (hash_type == ACE_SHA_TYPE_SHA1) ? > + ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH; > + reg |= ACE_HASH_STARTBIT_ON; > + writel(reg, &ace_sha_reg->hash_control); > + > + /* Enable FIFO mode */ > + writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode); > + > + /* Set message length */ > + writel(buf_len, &ace_sha_reg->hash_msgsize_low); > + writel(0, &ace_sha_reg->hash_msgsize_high); > + > + /* Set HRDMA */ > + writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas); > + writel(buf_len, &ace_sha_reg->fc_hrdmal); > + > + start = get_timer(0); > + > + while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) == > + ACE_HASH_MSGDONE_OFF) { > + if (get_timer(start) > TIMEOUT_MS) { > + debug("%s: Timeout waiting for ACE\n", __func__); > + return -ETIMEDOUT; > + } > + } > + > + /* Clear MSG_DONE bit */ > + writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status); > + > + /* Read hash result */ > + pdigest = (unsigned int *)pout; > + len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : > SHA256_SUM_LEN; > + > + for (i = 0; i < len; i += 4) { > + pdigest[i] = readl(&ace_sha_reg->hash_result[i]); > + pdigest[i + 1] = readl(&ace_sha_reg->hash_result[i + 1]); > + pdigest[i + 2] = readl(&ace_sha_reg->hash_result[i + 2]); > + pdigest[i + 3] = readl(&ace_sha_reg->hash_result[i + 3]); > + } Suggest: > + for (i = 0; i < len / 4; i++) > + pdigest[i] = readl(&ace_sha_reg->hash_result[i]); > + > + /* Clear HRDMA pending bit */ > + writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend); > + > + return 0; > +} > diff --git a/include/ace_sha.h b/include/ace_sha.h > new file mode 100644 > index 0000000..e005636 > --- /dev/null > +++ b/include/ace_sha.h > @@ -0,0 +1,42 @@ > +/* > + * Header file for SHA firmware > + * > + * Copyright (c) 2012 Samsung Electronics > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + */ > +#ifndef __ACE_FW_SHA1_H > +#define __ACE_FW_SHA1_H > + > +#define ACE_SHA_TYPE_SHA1 1 > +#define ACE_SHA_TYPE_SHA256 2 > + > +/** > + * Computes hash value of input pbuf using ACE > + * > + * @param in_addr A pointer to the input buffer > + * @param bufleni Byte length of input buffer > + * @param out_addr A pointer to the output buffer. When complete > + * 32 bytes are copied to pout[0]...pout[31]. Thus, a > user > + * should allocate at least 32 bytes at pOut in advance. > + * @param hash_type SHA1 or SHA256 > + * > + * @return 0 on Success, -1 on Failure (Timeout) > + */ > +int ace_sha_hash_digest(const uchar *in_addr, uint buflen, > + uchar *out_addr, uint hash_type); > + > +#endif > -- > 1.8.0 > Regards, Simon _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
