In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny <[email protected]> Cc: Mugunthan V N <[email protected]> Cc: Joe Hershberger <[email protected]> Cc: Tom Rini <[email protected]> --- drivers/net/cpsw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 39240d9..50167aa 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -914,7 +914,7 @@ static int cpsw_recv(struct eth_device *dev) void *buffer; int len; - cpsw_update_link(priv); + cpsw_check_link(priv); while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { invalidate_dcache_range((unsigned long)buffer, -- 1.7.10.4 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
