On Friday, July 04, 2014 at 12:19:13 PM, Masahiro Yamada wrote:
> The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
>
> This driver requires two CONFIG macros:
> - CONFIG_NAND_DENALI
> Define to enable this driver.
> - CONFIG_SYS_NAND_BAD_BLOCK_POS
> Specify bad block mark position in the oob space. Typically 0.
>
> Signed-off-by: Masahiro Yamada <yamad...@jp.panasonic.com>
> Cc: Chin Liang See <cl...@altera.com>
> Cc: Scott Wood <scottw...@freescale.com>
[...]
> +static void read_data_from_flash_mem(uint8_t *buf, int len)
> +{
> + int i;
> + uint32_t *buf32;
> +
> + /* transfer the data from the flash */
> + buf32 = (uint32_t *)buf;
> + for (i = 0; i < len / 4; i++)
> + *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
> +}
> +
> +int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
> +{
> + uint32_t addr, cmd;
> + static uint32_t page_count = 1;
> +
> + writel(ecc_en, denali_flash_reg + ECC_ENABLE);
> +
> + /* clear all bits of intr_status. */
> + writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
> +
> + addr = BANK(flash_bank) | page;
> +
> + /* setup the acccess type */
> + cmd = MODE_10 | addr;
> + index_addr(cmd, access_type);
> +
> + /* setup the pipeline command */
> + index_addr(cmd, 0x2000 | page_count);
Magic value 0x2000 should be fixed here.
> + cmd = MODE_01 | addr;
> + writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
Somehow, eventually, this should be migrated to "struct" based register access
instead of such offset computation. If you feel like doing it, that'd be nice
;-)
> + return wait_for_irq(INTR_STATUS__LOAD_COMP);
> +}
[...]
Thanks!
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