On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: > The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()' > function by trying different DLL adjustments and using the hardware > DQS gate training result as a feedback is a great source of inspiration, > but it just can't work properly the way it is implemented now. The fatal > problem of this implementation is that the DQS gating window can be > successfully found for almost every DLL delay adjustment setup that > gets tried. Thus making it unable to see any real difference between > 'good' and 'bad' settings. > > Also this code was supposed to be only activated by setting the highest > bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram > configuration). But none of the linux-sunxi devices has ever used it for > real. Basically, this code is just a dead weight. > > Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
