On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote: > In the case if the 'dram_para' struct does not specify the exact bus width > or chip density, just use a trial and error method to find a usable > configuration. > > Because all the major bugs in the DRAM initialization sequence are now > hopefully fixed, it should be safe to re-initialize the DRAM controller > multiple times until we get it configured right. The original Allwinner's > boot0 bootloader also used a similar autodetection trick. > > The DDR3 spec contains the package pinout and addressing table for different > possible chip densities. It appears to be impossible to distinguish between a > single chip with 16 I/O data lines and a pair of chips with 8 I/O data lines > in the case if they provide the same storage capacity. Because a single 16-bit > chip has a higher density than a pair of equivalent 8-bit chips, it has > stricter refresh timings. So in the case of doubt, we assume that 16-bit > chips are used. Additionally, only Allwinner A20 has all A0-A15 address > lines and can support densities up to 8192. The older Allwinner A10 and > Allwinner A13 can only support densities up to 4096. > > We deliberately leave out DDR2, dual-rank configurations and the special case > of a 8-bit chip with density 8192. None of these configurations seem to have > been ever used in real devices. And no new devices are likely to use these > exotic configurations (because only up to 2GB of RAM can be populated in any > case). > > This DRAM autodetection feature potentially allows to have a single low > performance fail-safe DDR3 initialiazation for a universal single bootloader > binary, which can be compatible with all Allwinner A10/A13/A20 based devices > (if the ifdefs are replaced with a runtime SoC type detection). > > Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
