On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote: > Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires > to wait for additional 500 us after the RESET pin is de-asserted. > > The DRAM controller takes care of this delay by itself, using a > configurable counter in the SDR_IDCR register. This works in the same > way on sun4i/sun5i/sun7i hardware (even the default register value > 0x00c80064 is identical). Except that the counter is ticking a bit > slower on sun7i (3 DRAM clock cycles instead of 2), resulting in > longer actual delays for the same settings. > > This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i > SoC variants and not just for sun7i alone. Also an explicit udelay(500) > is added immediately after DDR3 reset for extra safety. This is a > duplicated functionality. But since we don't have perfect documentation, > it may be reasonable to play safe. Half a millisecond boot time increase > is not that significant. Boot time can be always optimized later. > Preferebly by the people, who have the hardware equipment to check the > actual signals on the RESET and CKE lines and verify all the timings. > > The old code did not configure the SDR_IDCR register for sun4i/sun5i, > but performed the DDR3 reset very early for sun4i/sun5i. This resulted > in a larger time gap between the DDR3 reset and the DDR3 initialization > steps and reduced the chances of CKE delay timing violation to cause > real troubles. > > Signed-off-by: Siarhei Siamashka <siarhei.siamas...@gmail.com>
Acked-by: Ian Campbell <i...@hellion.org.uk> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot