On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote: > All the known Allwinner A10/A13/A20 devices are using just single rank > DDR3 memory. So don't pretend that we support DDR2 or more than one > rank, because nobody could ever test these configurations for real and > they are likely broken. Support for these features can be added back > in the case if such hardware actually exists. > > As part of this code cleanup, also replace division by 1024 with > division by 1000 for the refresh timing calculations. This allows > to use the original non-skewed tRFC timing table from the DRR3 spec > and make code less confusing. > > Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Ian Campbell <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
