On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut <[email protected]> wrote: > On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote: >> mx6 is an armv7 which has 64-byte cacheline size. >> >> Without this fix we are not able to get the FEC driver to work on mx6solox. >> >> 64-byte cacheline is also used by the kernel on ARMv7, so fix it >> accordingly. > > It's not a kernel thing, it's architecture thing. Otherwise, > > Acked-by: Marek Vasut <[email protected]>
Actually the CortexA9 manual says: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Caccifbd.html "The cache line length is eight words." and the mx6q RM says: 12.5.4.1 L1 features .... • Eight 32-bit words per cache line So the current CONFIG_SYS_CACHELINE_SIZE of 32 is correct for mx6. In kernel we use 64-bytes of cache line for armv7 though: config ARM_L1_CACHE_SHIFT_6 bool default y if CPU_V7 help Setting ARM L1 cache line size to 64 Bytes. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
