Hi Benoît, On Thu, Aug 21, 2014 at 5:13 PM, Benoît Thébaudeau <[email protected]> wrote:
> Yes, it's always 32 bytes for Cortex-A9. But does mx6solox really have > a standard Cortex-A9 core like all the currently released i.MX6 SoCs > (which seems to be the case according to > http://lwn.net/Articles/598434/), or a Cortex-A9 implementation with > non-standard parameters tuned by Freescale, or even another core like > a Cortex-A8? It is a Cortex-A9 on mx6solox (there is also a Cortex-M4) and its manual also states 32 bytes of cache line. I am trying to get more information about the 64-bit alignment requirement on FEC RX DMA. Regards, Fabio Estevam _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
