> -----Original Message----- > From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net] > Sent: Thursday, September 18, 2014 7:25 PM > To: Tang Yuantian-B29983 > Cc: Wang Huan-B18965; Lu Jingchang-B35083; Jin Zhengxiong-R64188; > Kushwaha Prabhakar-B32579; u-boot@lists.denx.de > Subject: Re: [PATCH] arm: ls102xa: Fixed a register definition error > > Hi Tang, > > On Thu, 18 Sep 2014 17:12:06 +0800, Tang Yuantian > <yuantian.t...@freescale.com> wrote: > > > There are 8 SCFG_SPARECR registers in SCFG memory block, not just one. > > > > Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com> > > --- > > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > > b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > > index 7995fe2..b5db720 100644 > > --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > > +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > > @@ -182,7 +182,7 @@ struct ccsr_scfg { > > u32 etsecmcr; > > u32 sdhciovserlcr; > > u32 resv14[61]; > > - u32 sparecr; > > + u32 sparecr[8]; > > }; > > > > /* Clocking */ > > Obviously the original code was not problematic as sparecr was not used. Is > your > change dictated by a patch or series that you are preparing and that will use > sparecr? > Yes, they will be used by deep sleep patches I am preparing.
Thanks, Yuantian > Amicalement, > -- > Albert. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot