This commit adds on-chip I2C driver used on some old Panasonic
UniPhier SoCs.

Signed-off-by: Masahiro Yamada <[email protected]>
---

 drivers/i2c/Kconfig        |  14 +++
 drivers/i2c/Makefile       |   1 +
 drivers/i2c/i2c-uniphier.c | 225 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/i2c/i2c-uniphier.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index e69de29..6a479ef 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -0,0 +1,14 @@
+config DM_I2C
+       bool "Enable Driver Model for I2C drivers"
+       depends on DM
+       help
+         If you want to use driver model for I2C drivers, say Y.
+         To use legacy I2C drivers, say N.
+
+config SYS_I2C_UNIPHIER
+       bool "UniPhier I2C driver"
+       depends on ARCH_UNIPHIER && DM_I2C
+       default y
+       help
+         Support for Panasonic UniPhier I2C controller driver.  This I2C
+         controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 6f3c86c..e2fcd24 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -31,4 +31,5 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o 
i2c-emul-uclass.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
+obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
 obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
new file mode 100644
index 0000000..05035ac
--- /dev/null
+++ b/drivers/i2c/i2c-uniphier.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <dm/device.h>
+#include <dm/root.h>
+#include <i2c.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_DTRM       0x00    /* data transmission */
+#define                I2C_DTRM_STA    (1 << 10)
+#define                I2C_DTRM_STO    (1 << 9)
+#define                I2C_DTRM_NACK   (1 << 8)
+#define                I2C_DTRM_RD     (1 << 0)
+#define I2C_DREC       0x04    /* data reception */
+#define                I2C_DREC_STS    (1 << 12)
+#define                I2C_DREC_LRB    (1 << 11)
+#define                I2C_DREC_LAB    (1 << 9)
+#define I2C_MYAD       0x08
+#define I2C_CLK                0x0c
+#define I2C_BRST       0x10    /* bus reset */
+#define                I2C_BRST_FOEN   (1 << 1)
+#define                I2C_BRST_BRST   (1 << 0)
+#define I2C_HOLD       0x14
+#define I2C_BSTS       0x18
+#define I2C_NOISE      0x1c
+#define I2C_SETUP      0x20
+
+#define IOBUS_FREQ     100000000
+
+struct uniphier_i2c_dev {
+       void __iomem *base;             /* register base */
+       unsigned long input_clk;        /* master clock (Hz) */
+       unsigned long wait_us;          /* wait for every byte transfer (us) */
+};
+
+static int uniphier_i2c_probe(struct udevice *dev)
+{
+       fdt_addr_t addr;
+       fdt_size_t size;
+       struct uniphier_i2c_dev *priv = dev_get_priv(dev);
+
+       addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+
+       priv->base = map_sysmem(addr, size);
+
+       if (!priv->base)
+               return -ENOMEM;
+
+       priv->input_clk = IOBUS_FREQ;
+
+       /* deassert reset */
+       writel(0x3, priv->base + I2C_BRST);
+
+       return 0;
+}
+
+static int uniphier_i2c_remove(struct udevice *dev)
+{
+       struct uniphier_i2c_dev *priv = dev_get_priv(dev);
+
+       unmap_sysmem(priv->base);
+
+       return 0;
+}
+
+static int uniphier_i2c_child_pre_probe(struct udevice *dev)
+{
+       struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
+
+       if (dev->of_offset == -1)
+               return 0;
+       return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+                                          i2c_chip);
+}
+
+static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm)
+{
+       writel(dtrm, dev->base + I2C_DTRM);
+
+       /*
+        * U-Boot does not have a good support of interrupt.
+        * Wait for a while.
+        */
+       udelay(dev->wait_us);
+
+       return readl(dev->base + I2C_DREC);
+}
+
+static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop)
+{
+       int ret = 0;
+       u32 drec;
+
+       drec = send_and_recv_byte(dev, dtrm);
+
+       if (drec & I2C_DREC_LAB) {
+               debug("uniphier_i2c: bus arbitration failed\n");
+               *stop = false;
+               ret = -EREMOTEIO;
+       }
+       if (drec & I2C_DREC_LRB) {
+               debug("uniphier_i2c: slave did not return ACK\n");
+               ret = -EREMOTEIO;
+       }
+       return ret;
+}
+
+static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev,
+                                uint addr, uint len, const u8 *buf)
+{
+       int ret;
+       bool stop = true;
+
+       ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, &stop);
+       if (ret < 0)
+               goto fail;
+
+       while (len--) {
+               ret = send_byte(dev, I2C_DTRM_NACK | *buf++, &stop);
+               if (ret < 0)
+                       goto fail;
+       }
+
+fail:
+       if (stop)
+               writel(I2C_DTRM_STO | I2C_DTRM_NACK, dev->base + I2C_DTRM);
+
+       return ret;
+}
+
+static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev,
+                               uint addr, uint len, u8 *buf)
+{
+       int ret;
+       bool stop = true;
+
+       ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK |
+                       I2C_DTRM_RD | addr << 1, &stop);
+       if (ret < 0)
+               goto fail;
+
+       while (len--)
+               *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK);
+
+fail:
+       if (stop)
+               writel(I2C_DTRM_STO | I2C_DTRM_NACK, dev->base + I2C_DTRM);
+
+       return ret;
+}
+
+static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+                            int nmsgs)
+{
+       int ret = 0;
+       struct uniphier_i2c_dev *dev = dev_get_priv(bus);
+
+       for (; nmsgs > 0; nmsgs--, msg++) {
+               if (msg->flags & I2C_M_RD)
+                       ret = uniphier_i2c_receive(dev, msg->addr,
+                                                  msg->len, msg->buf);
+               else
+                       ret = uniphier_i2c_transmit(dev, msg->addr,
+                                                   msg->len, msg->buf);
+
+               if (ret < 0)
+                       break;
+       }
+
+       return ret;
+}
+
+static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+       struct uniphier_i2c_dev *priv = dev_get_priv(bus);
+
+       /* max supported frequency is 400 kHz */
+       if (speed > 400000)
+               return -EINVAL;
+
+       /* bus reset: make sure the bus is idle when change the freqency */
+       writel(0x1, priv->base + I2C_BRST);
+
+       writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
+              priv->base + I2C_CLK);
+
+       writel(0x3, priv->base + I2C_BRST);
+
+       priv->wait_us = 20000000 / speed;
+
+       return 0;
+}
+
+
+static const struct dm_i2c_ops uniphier_i2c_ops = {
+       .xfer = uniphier_i2c_xfer,
+       .set_bus_speed = uniphier_i2c_set_bus_speed,
+};
+
+static const struct udevice_id uniphier_i2c_of_match[] = {
+       { .compatible = "panasonic,uniphier-i2c" },
+       {},
+};
+
+U_BOOT_DRIVER(uniphier_i2c) = {
+       .name = "uniphier-i2c",
+       .id = UCLASS_I2C,
+       .of_match = uniphier_i2c_of_match,
+       .probe = uniphier_i2c_probe,
+       .remove = uniphier_i2c_remove,
+       .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+       .child_pre_probe = uniphier_i2c_child_pre_probe,
+       .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev),
+       .ops = &uniphier_i2c_ops,
+};
-- 
1.9.1

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