Hi Simon,
On Tue, 23 Dec 2014 12:58:12 -0700 Simon Glass <[email protected]> wrote: > Hi Masahiro, > > On 22 December 2014 at 03:58, Masahiro Yamada <[email protected]> > wrote: > > This commit adds on-chip I2C driver used on newer SoCs of Panasonic > > UniPhier platform. > > > > Signed-off-by: Masahiro Yamada <[email protected]> > > For driver model bits: > > Reviewed-by: Simon Glass <[email protected]> > > A few comments below. > > > --- > > > > drivers/i2c/Kconfig | 8 + > > drivers/i2c/Makefile | 1 + > > drivers/i2c/i2c-uniphier-f.c | 355 > > +++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 364 insertions(+) > > create mode 100644 drivers/i2c/i2c-uniphier-f.c > > > > diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig > > index 6a479ef..e75c1ff 100644 > > --- a/drivers/i2c/Kconfig > > +++ b/drivers/i2c/Kconfig > > @@ -12,3 +12,11 @@ config SYS_I2C_UNIPHIER > > help > > Support for Panasonic UniPhier I2C controller driver. This I2C > > controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. > > + > > +config SYS_I2C_UNIPHIER_F > > + bool "UniPhier I2C with FIFO driver" > > + depends on ARCH_UNIPHIER && DM_I2C > > + default y > > + help > > + Support for Panasonic UniPhier I2C with FIFO controller driver. > > + This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. > > diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile > > index e2fcd24..0e4c9f4 100644 > > --- a/drivers/i2c/Makefile > > +++ b/drivers/i2c/Makefile > > @@ -32,4 +32,5 @@ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o > > obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o > > obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o > > obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o > > +obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o > > obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o > > diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c > > new file mode 100644 > > index 0000000..14a7f1c > > --- /dev/null > > +++ b/drivers/i2c/i2c-uniphier-f.c > > @@ -0,0 +1,355 @@ > > +/* > > + * Copyright (C) 2014 Panasonic Corporation > > + * Author: Masahiro Yamada <[email protected]> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +/* #define DEBUG */ > > + > > +#include <common.h> > > +#include <linux/types.h> > > +#include <asm/io.h> > > +#include <asm/errno.h> > > +#include <dm/device.h> > > +#include <dm/root.h> > > +#include <i2c.h> > > +#include <fdtdec.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define I2C_CR 0x00 /* control register */ > > struct i2c_reg { > u32 cr; > u32 fifo; > ... > } I answered in the other reply. > > +#define I2C_CR_MST (1 << 3) /* master mode */ > > +#define I2C_CR_STA (1 << 2) /* start condition > > */ > > +#define I2C_CR_STO (1 << 1) /* stop condition */ > > +#define I2C_CR_NACK (1 << 0) /* not ACK */ > > + > > +#define I2C_DTTX 0x04 /* send FIFO */ > > +#define I2C_DTRX 0x04 /* receive FIFO */ > > +#define I2C_DTTX_CMD (1 << 8) /* send command > > (slave addr) */ > > +#define I2C_DTTX_RD (1 << 0) /* read */ > > +#define I2C_SLAD 0x0c /* slave address */ > > +#define I2C_CYC 0x10 /* clock cycle control */ > > +#define I2C_LCTL 0x14 /* clock low period control */ > > +#define I2C_SSUT 0x18 /* restart/stop setup time control > > */ > > +#define I2C_DSUT 0x1c /* data setup time control */ > > +#define I2C_INT 0x20 /* interrupt status */ > > +#define I2C_IE 0x24 /* interrupt enable */ > > +#define I2C_IC 0x28 /* interrupt clear */ > > +#define I2C_INT_TE (1 << 9) /* TX FIFO empty */ > > +#define I2C_INT_RB (1 << 4) /* received > > specified bytes */ > > +#define I2C_INT_NA (1 << 2) /* no answer */ > > +#define I2C_INT_AL (1 << 1) /* arbitration lost > > */ > > +#define I2C_SR 0x2c /* status register */ > > +#define I2C_SR_DB (1 << 12) /* device busy */ > > +#define I2C_SR_BB (1 << 8) /* bus busy */ > > +#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */ > > +#define I2C_SR_RNE (1 << 2) /* Rx FIFO not > > empty */ > > +#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full > > */ > > +#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */ > > +#define I2C_RST 0x34 /* reset control */ > > +#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */ > > +#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */ > > +#define I2C_RST_RST (1 << 0) /* forcible bus > > reset */ > > +#define I2C_TBC 0x40 > > +#define I2C_RBC 0x44 > > +#define I2C_TBCM 0x48 > > +#define I2C_RBCM 0x4c > > +#define I2C_BRST 0x50 /* bus reset */ > > +#define I2C_BRST_FOEN (1 << 1) /* normal operation > > */ > > +#define I2C_BRST_RSCLO (1 << 0) /* release SCL low > > fixing */ > > + > > +#define FIOCLK 50000000 > > + > > +struct uniphier_fi2c_dev { > > + void __iomem *base; /* register base */ > > Should use register access in U-Boot. > > > + unsigned long fioclk; /* internal operation clock */ > > + unsigned long wait_us; /* wait for every byte transfer > > (us) */ > > This is really a timeout isn't it? Yes. I will fix this comment. Best Regards Masahiro Yamada _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
