On Thu, May 28, 2015 at 11:22 PM, Maxime Ripard <maxime.rip...@free-electrons.com> wrote: > On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote: >> This adds PSCI support for sun6i. So far it only supports >> the PWR_ON method. >> >> Signed-off-by: Chen-Yu Tsai <w...@csie.org> >> --- >> arch/arm/cpu/armv7/sunxi/Makefile | 1 + >> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 >> ++++++++++++++++++++++++++++++++++ >> 2 files changed, 277 insertions(+) >> create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S >> >> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile >> b/arch/arm/cpu/armv7/sunxi/Makefile >> index 85fbc85..4b783e0 100644 >> --- a/arch/arm/cpu/armv7/sunxi/Makefile >> +++ b/arch/arm/cpu/armv7/sunxi/Makefile >> @@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER) += pmic_bus.o >> >> ifndef CONFIG_SPL_BUILD >> ifdef CONFIG_ARMV7_PSCI >> +obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o >> obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o >> endif >> endif >> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S >> b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S >> new file mode 100644 >> index 0000000..2516804 >> --- /dev/null >> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S >> @@ -0,0 +1,276 @@ >> +/* >> + * Copyright (C) 2015 - Chen-Yu Tsai >> + * Author: Chen-Yu Tsai <w...@csie.org> >> + * >> + * Based on psci_sun7i.S by Marc Zyngier <marc.zyng...@arm.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License >> + * along with this program. If not, see <http://www.gnu.org/licenses/>. >> + */ >> + >> +#include <config.h> >> +#include <asm/gic.h> >> +#include <asm/macro.h> >> +#include <asm/psci.h> >> +#include <asm/arch/cpu.h> >> + >> +/* >> + * Memory layout: >> + * >> + * SECURE_RAM to text_end : >> + * ._secure_text section >> + * text_end to ALIGN_PAGE(text_end): >> + * nothing >> + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) >> + * 1kB of stack per CPU (4 CPUs max). >> + */ >> + >> + .pushsection ._secure.text, "ax" >> + >> + .arch_extension sec >> + >> +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) >> +#define TEN_MS (10 * ONE_MS) >> +#define GICD_BASE 0x1c81000 >> +#define GICC_BASE 0x1c82000 >> + >> +.macro timer_wait reg, ticks >> + @ Program CNTP_TVAL >> + movw \reg, #(\ticks & 0xffff) >> + movt \reg, #(\ticks >> 16) >> + mcr p15, 0, \reg, c14, c2, 0 >> + isb >> + @ Enable physical timer, mask interrupt >> + mov \reg, #3 >> + mcr p15, 0, \reg, c14, c2, 1 >> + @ Poll physical timer until ISTATUS is on >> +1: isb >> + mrc p15, 0, \reg, c14, c2, 1 >> + ands \reg, \reg, #4 >> + bne 1b >> + @ Disable timer >> + mov \reg, #0 >> + mcr p15, 0, \reg, c14, c2, 1 >> + isb >> +.endm >> + > > I think I saw some patch to factorize that out. In the Tegra K1 PSCI > patches iirc.
Waiting for v2: https://patchwork.ozlabs.org/patch/471694/ >> +.globl psci_fiq_enter >> +psci_fiq_enter: >> + push {r0-r12} >> + >> + @ Switch to secure >> + mrc p15, 0, r7, c1, c1, 0 >> + bic r8, r7, #1 >> + mcr p15, 0, r8, c1, c1, 0 >> + isb >> + >> + @ Validate reason based on IAR and acknowledge >> + movw r8, #(GICC_BASE & 0xffff) >> + movt r8, #(GICC_BASE >> 16) >> + ldr r9, [r8, #GICC_IAR] >> + movw r10, #0x3ff >> + movt r10, #0 >> + cmp r9, r10 @ skip spurious interrupt 1023 >> + beq out >> + movw r10, #0x3fe @ ...and 1022 > > Maybe we could add some defines for these spurious interrupts values ? >From the GIC spec: The read returns a spurious interrupt ID of 1023 if any of the following apply: - forwarding of interrupts by the Distributor to the CPU interface is disabled - signaling of interrupts by the CPU interface to the connected processor is disabled - no pending interrupt on the CPU interface has sufficient priority for the interface to signal it to the processor. Likewise, 1022 means group 0 secure interrupts aren't forwarded to the processor. So my understanding is that 1022/1023 just means there's nothing for the processor to process. Maybe a note referring to the spec would be enough? >> +.globl psci_arch_init >> +psci_arch_init: >> + mov r6, lr >> + >> + movw r4, #(GICD_BASE & 0xffff) >> + movt r4, #(GICD_BASE >> 16) >> + >> + ldr r5, [r4, #GICD_IGROUPRn] >> + bic r5, r5, #(1 << 15) @ SGI15 as Group-0 >> + str r5, [r4, #GICD_IGROUPRn] >> + >> + mov r5, #0 @ Set SGI15 priority to 0 >> + strb r5, [r4, #(GICD_IPRIORITYRn + 15)] >> + >> + add r4, r4, #0x1000 @ GICC address >> + >> + mov r5, #0xff >> + str r5, [r4, #GICC_PMR] @ Be cool with non-secure >> + >> + ldr r5, [r4, #GICC_CTLR] >> + orr r5, r5, #(1 << 3) @ Switch FIQEn on >> + str r5, [r4, #GICC_CTLR] >> + >> + mrc p15, 0, r5, c1, c1, 0 @ Read SCR >> + orr r5, r5, #4 @ Enable FIQ in monitor mode >> + bic r5, r5, #1 @ Secure mode >> + mcr p15, 0, r5, c1, c1, 0 @ Write SCR >> + isb >> + >> + bl psci_get_cpu_id @ CPU ID => r0 >> + bl psci_get_cpu_stack_top @ stack top => r0 >> + mov sp, r0 >> + >> + bx r6 >> + >> + .globl psci_text_end > > Isn't it exactly the same function than the A20's? Maybe that can be > shared? Good idea. This might even be shared by some other platforms. "psci_text_end" should always be linked in last though. ChenYu _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
