Dear Poonam Aggrwal,
In message <[email protected]> you
wrote:
> The code base is generic to add more P1_P2 RDB platforms support as and when
> required.
> The folder and file names are such that they can cater to future SOCs of P1/P2
> family.
> P1 P2 processors are 85xx platforms which fall in Low End and Ultra Low End
> band of Freescale QorIQ series.
>
> Tested the following on P2020RDB:
> 1. eTSECs(1/2/3)
> 2. DDR, NAND, NOR, I2C, PCIe, etc
>
> Signed-off-by: Poonam Aggrwal <[email protected]>
> ---
> -Based of u-boot version 2009.08-rc1
> -Incorporated comments of Wolfgang and Kumar Gala.
> -get_mem_size has not been because the board has onboard fixed memory with
> pre-known memory size.
I won't object because it's your design descision after all, but I
would like to point out that the use of get_ram_size() is not only
useful to auto-detect the size of the RAM, but also to perform a
(very fast, yet pretty efficient) memory test. The test is fast
enough to be used as part of the regular power-on / reset sequence,
and it still covers 90% or more of all memory problems - this is
especially useful to make sure you have working hardware.
So I always recomment to enable the feature - unless you really have
to save a few milliseconds on boot time.
...
> +P2020RDB_config: unconfig
> + @mkdir -p $(obj)include
> + @echo "#define CONFIG_MP" >>$(obj)include/config.h ;
> + @$(XECHO) "... setting CONFIG_MP." ;
Is this really needed? I'd like to keep such stuff out of the
Makefile.
> +#define DATARATE_400MHZ 400000000
> +#define DATARATE_534MHZ 534000000
534 MHz? Not 533.333 = 4 x 133.333 ?
> +#define DATARATE_667MHZ 667000000
> +#define DATARATE_800MHZ 800000000
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
> + .cs[0].bnds = 0x0000003F,
> + .cs[0].config = 0x80014202,
> + .cs[0].config_2 = 0x00000000,
> + .timing_cfg_3 = 0x00010000,
> + .timing_cfg_0 = 0x00260802,
> + .timing_cfg_1 = 0x39355322,
> + .timing_cfg_2 = 0x1f9048ca,
...
These magic numbers should probably be explained / commented /
replaced by some #define's ?
> +phys_size_t fixed_sdram (void)
> +{
> + volatile ccsr_ddr_t *ddr= (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
> + sys_info_t sysinfo;
> + char buf[32];
> + phys_size_t dram_size;
> +
> + get_sys_info(&sysinfo);
> + printf("Configuring DDR for %s MT/s data rate\n",
> + strmhz(buf, sysinfo.freqDDRBus));
> +
> + if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
> + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
Copy & paste error? &ddr_cfg_regs_400 ?
> + else if(sysinfo.freqDDRBus <= DATARATE_534MHZ)
> + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
Ditto?
> + else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
> + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
Ditto?
> + else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
> + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
else ???
> +int checkboard (void)
> +{
> + u32 val, temp;
> + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> + char board_rev = 0;
> + struct cpu_type *cpu;
> +
> + val = pgpio->gpdat;
> + temp = val & BOARDREV_MASK;
> + if (temp == BOARDREV_C)
> + board_rev = 'C';
> + else if (temp == BOARDREV_B)
> + board_rev = 'B';
> + else
> + panic ("!!Unexpected Board REV detected!!\n");
It might be helpful to print here _which_ unexpacted value you got.
This saves at one debug cycle.
> + cpu = gd->cpu;
> + printf ("Board: %sRDB Rev%c, System ID: 0x%02x, "
> + "System Version: 0x%02x\n", cpu->name,
> + board_rev, 0, 0);
> +
> +/* Bringing the following peripherals out of reset via GPIOs
> + * 0= reset and 1= out of reset
...
Incorrect multiline comment style.
> +++ b/board/freescale/p1_p2_rdb/pci.c
> @@ -0,0 +1,177 @@
..
> +#include <common.h>
> +#include <command.h>
> +#include <pci.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_pci.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +
Only one blank line here in both cases, please.
> +#ifdef CONFIG_PCIE1
> +static struct pci_controller pcie1_hose;
> +#endif
> +
> +#ifdef CONFIG_PCIE2
> +static struct pci_controller pcie2_hose;
> +#endif
> +
> +int first_free_busno=0;
> +void pci_init_board(void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> + uint devdisr = gur->devdisr;
> + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
> + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
> +
> + volatile ccsr_fsl_pci_t *pci;
> + struct pci_controller *hose;
> + int pcie_ep, pcie_configured;
> + struct pci_region *r;
> +
> + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
> + devdisr, io_sel, host_agent);
> +
> + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
> + printf (" eTSEC2 is in sgmii mode.\n");
> +
> +#ifdef CONFIG_PCIE2
> + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
> + hose = &pcie2_hose;
> + pcie_ep = (host_agent == 2) || (host_agent == 4) ||
> + (host_agent == 6) || (host_agent == 0);
> + pcie_configured = (io_sel == 0xE);
> + r = hose->regions;
> +
> + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
> + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
> + pcie_ep ? "End Point": "Root Complex", (uint)pci);
> + if (pci->pme_msg_det) {
> + pci->pme_msg_det = 0xffffffff;
> + debug (" with errors. Clearing. Now 0x%08x",
> + pci->pme_msg_det);
> + }
> + printf ("\n");
> +
> + /* inbound */
> + r += fsl_pci_setup_inbound_windows(r);
> +
> + /* outbound memory */
> + pci_set_region(r++,
> + CONFIG_SYS_PCIE2_MEM_BUS,
> + CONFIG_SYS_PCIE2_MEM_PHYS,
> + CONFIG_SYS_PCIE2_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + /* outbound io */
> + pci_set_region(r++,
> + CONFIG_SYS_PCIE2_IO_BUS,
> + CONFIG_SYS_PCIE2_IO_PHYS,
> + CONFIG_SYS_PCIE2_IO_SIZE,
> + PCI_REGION_IO);
> +
> + hose->region_count = r - hose->regions;
> + hose->first_busno=first_free_busno;
> + pci_setup_indirect(hose, (int) &pci->cfg_addr,
> + (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> + first_free_busno=hose->last_busno+1;
> + printf (" PCIE2 on bus %02x - %02x\n",
> + hose->first_busno,hose->last_busno);
> +
> + } else {
> + printf (" PCIE2: disabled\n");
> + }
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
> +#endif
> +#ifdef CONFIG_PCIE1
> + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
> + hose = &pcie1_hose;
...
This code repeast mit minimal differences what you have for
CONFIG_PCIE2; how about moving one copy of this code into a function
which gets calles twice with appropriate arguments?
> diff --git a/doc/README.p2020rdb b/doc/README.p2020rdb
> new file mode 100644
> index 0000000..a9c807b
> --- /dev/null
> +++ b/doc/README.p2020rdb
> @@ -0,0 +1,143 @@
> +Overview
> +--------
> +P2020RDB is a Low End Dual core platform supporting the P2020 processor of
> QorIQ
> +series.
Please use shorter lines for test files - some 68...72 characters
should not be exceeded.
...
> + linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
> +
> +
Only one blank line, please.
> +Booting Linux
> +-------------
> +
> +Place a linux uImage in the TFTP disk area.
> +
> + tftp 1000000 uImage.p2020rdb
> + tftp 2000000 rootfs.ext2.gz.uboot
> + tftp c00000 p2020rdb.dtb
> + bootm 1000000 2000000 c00000
> +
> +
> +
Only one blank line, please.
> +Implementing AMP(Asymmetric MultiProcessing)
> +---------------------------------------------
> +1. Build kernel image for core0:
> +
> + a. $ make 85xx/p1_p2_rdb_defconfig
> +
> + b. $ make menuconfig
> + - un-select "Processor support"->"Symetric multi-processing support"
> +
> + c. $ make uImage
> +
> + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
> +
> +2. Build kernel image for core1:
> +
> + a. $ make 85xx/p1_p2_rdb_defconfig
> +
> + b. $ make menuconfig
> + - Un-select "Processor support"->"Symetric multi-processing support"
> + - Select "Advanced setup" -> " Prompt for advanced kernel
> + configuration options"
> + - Select "Set physical address where the kernel is loaded" and
> + set it to 0x20000000, asssuming core1 will start from 512MB.
> + - Select "Set custom page offset address"
> + - Select "Set custom kernel base address"
> + - Select "Set maximum low memory"
> + - "Exit" and save the selection.
> +
> + c. $ make uImage
> +
> + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
> +
> +3. Create dtb for core0:
> +
> + $ dtc -I dts -O dtb -f -b 0
> arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
> /tftpboot/p2020rdb_camp_core0.dtb
> +
> +4. Create dtb for core1:
> +
> + $ dtc -I dts -O dtb -f -b 1
> arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
> /tftpboot/p2020rdb_camp_core1.dtb
> +
> +5. Bring up two cores separately:
> +
> + a. Power on the board, under u-boot prompt:
> + => setenv <serverip>
> + => setenv <ipaddr>
> + => setenv bootargs root=/dev/ram rw console=ttyS0,115200
> + b. Bring up core1's kernel first:
> + => setenv bootm_low 0x20000000
> + => setenv bootm_size 0x10000000
> + => tftp 21000000 uImage.core1
> + => tftp 22000000 ramdiskfile
> + => tftp 20c00000 p2020rdb_camp_core1.dtb
> + => interrupts off
> + => bootm start 21000000 22000000 20c00000
> + => bootm loados
> + => bootm ramdisk
> + => bootm fdt
> + => fdt boardsetup
> + => fdt chosen $initrd_start $initrd_end
> + => bootm prep
> + => cpu 1 release $bootm_low - $fdtaddr -
> + c. Bring up core0's kernel(on the same u-boot console):
> + => setenv bootm_low 0
> + => setenv bootm_size 0x20000000
> + => tftp 1000000 uImage.core0
> + => tftp 2000000 ramdiskfile
> + => tftp c00000 p2020rdb_camp_core0.dtb
> + => bootm 1000000 2000000 c00000
> +
> +Please note only core0 will run u-boot, core1 starts kernel directly after
> +"cpu release" command is issued.
> diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
> new file mode 100644
> index 0000000..cff2de6
> --- /dev/null
> +++ b/include/configs/P1_P2_RDB.h
> @@ -0,0 +1,559 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * P1 P2 RDB board configuration file
> + * This file is intends to address a set of Low End and Ultra Low End
> + * Freescale SOCs of QorIQ series(RDB platforms).
> + * Currently only P2020RDB
> + *
> + */
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/* High Level Configuration Options */
> +#define CONFIG_BOOKE 1 /* BOOKE */
> +#define CONFIG_E500 1 /* BOOKE e500 family */
> +#define CONFIG_MPC85xx 1 /*
> MPC8540/60/55/41/48/P1020/P2020,etc*/
> +#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
> +#define CONFIG_PCI 1 /* Enable PCI/PCIE */
> +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
> +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
> +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
> +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
> +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
> +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
> +#define CONFIG_TSEC_ENET /* tsec ethernet support */
> +#define CONFIG_ENV_OVERWRITE
> +
> +
> +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
> +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
> +
> +/*
> + * These can be toggled for performance analysis, otherwise use default.
> + */
> +#define CONFIG_L2_CACHE /* toggle L2 cache */
> +#define CONFIG_BTB /* toggle branch predition */
> +
> +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
> +
> +#define CONFIG_ENABLE_36BIT_PHYS 1
> +
> +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END 0x1fffffff
> +#define CONFIG_PANIC_HANG /* do not reset board on panic */
> +
> +/*
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + */
> +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
> +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
> +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical
> addr of */
> + /* CCSRBAR */
> +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
> + /* CONFIG_SYS_IMMR */
> +
> +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
> +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
> +
> +/* DDR Setup */
> +#define CONFIG_FSL_DDR2
> +#undef CONFIG_FSL_DDR_INTERACTIVE
> +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
> +#undef CONFIG_DDR_DLL
> +
> +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
> +
> +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
> +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
> +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_NUM_DDR_CONTROLLERS 1
> +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
> +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
> +
> +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
> +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
> +#define CONFIG_SYS_DDR_SBE 0x00FF0000
> +
> +#define CONFIG_SYS_DDR_TLB_START 9
> +
> +/*
> + * Memory map
> + *
> + * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
> + * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
> + * 0xffc2_0000 0xffc5_ffff PCI IO range 256K
> non-cacheable
> + *
> + * Localbus cacheable (TBD)
> + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
> + *
> + * Localbus non-cacheable
> + * 0xef00_0000 0xefff_ffff FLASH 16M
> non-cacheable
> + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
> + * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
> + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable
> TLB0
> + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
> + */
> +
> +/*
> + * Local Bus Definitions
> + */
> +#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of
> FLASH 16M */
> +
> +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
> +
> +#define CONFIG_FLASH_BR_PRELIM
> (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
> + BR_PS_16 | BR_V)
> +#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
> +
> +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
> +#define CONFIG_SYS_FLASH_QUIET_TEST
> +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
> +
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
> +#undef CONFIG_SYS_FLASH_CHECKSUM
> +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> +
> +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
> +
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_EMPTY_INFO
> +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
> +
> +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
> +
> +
> +#define CONFIG_SYS_INIT_RAM_LOCK 1
> +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
> +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in
> RAM */
> +
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
> +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
> + - CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> +
> +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB
> for Mon*/
> +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for
> malloc*/
> +
> +#define CONFIG_SYS_NAND_BASE 0xffa00000
> +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
> +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS 1
> +#define CONFIG_MTD_NAND_VERIFY_WRITE
> +#define CONFIG_CMD_NAND 1
> +#define CONFIG_NAND_FSL_ELBC 1
> +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
> +
> +/* NAND flash config */
> +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
> + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
> + | BR_PS_8 /* Port Size = 8 bit */ \
> + | BR_MS_FCM /* MSEL = FCM */ \
> + | BR_V) /* valid */
> +
> +#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K
> */ \
> + | OR_FCM_CSCT \
> + | OR_FCM_CST \
> + | OR_FCM_CHT \
> + | OR_FCM_SCY_1 \
> + | OR_FCM_TRLX \
> + | OR_FCM_EHTR)
> +
> +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
> +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
> +#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
> +#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
> +
> +#define CONFIG_SYS_VSC7385_BASE 0xffb00000
> +
> +#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
> +
> +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 |
> BR_V)
> +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT |
> OR_GPCM_XACS | \
> + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
> + OR_GPCM_EHTR | OR_GPCM_EAD)
> +
> +/* Serial Port - controlled on board with jumper J8
> + * open - index 2
> + * shorted - index 1
> + */
> +#define CONFIG_CONS_INDEX 1
> +//#define CONFIG_CONS_INDEX 2
> +#undef CONFIG_SERIAL_SOFTWARE_FIFO
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> +
> +#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
> +
> +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
> +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
> +
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER
> +#ifdef CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +/*
> + * Pass open firmware flat tree
> + */
> +#define CONFIG_OF_LIBFDT 1
> +#define CONFIG_OF_BOARD_SETUP 1
> +#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> +
> +#define CONFIG_SYS_64BIT_VSPRINTF 1
> +#define CONFIG_SYS_64BIT_STRTOUL 1
> +
> +/* new uImage format support */
> +#define CONFIG_FIT 1
> +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
> +
> +/* I2C */
> +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
> +#define CONFIG_HARD_I2C /* I2C with hardware support */
> +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_I2C_CMD_TREE
> +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
> +#define CONFIG_SYS_I2C_SLAVE 0x7F
> +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these
> addrs */
> +#define CONFIG_SYS_I2C_OFFSET 0x3000
> +#define CONFIG_SYS_I2C2_OFFSET 0x3100
> +
> +/*
> + * I2C2 EEPROM
> + */
> +#define CONFIG_ID_EEPROM
> +#ifdef CONFIG_ID_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_NXID
> +#endif
> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
> +#define CONFIG_SYS_EEPROM_BUS_NUM 1
> +
> +#define CONFIG_RTC_DS1337
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> +/*
> + * General PCI
> + * Memory space is mapped 1-1, but I/O space must start from 0.
> + */
> +
> +/* controller 2, Slot 2, tgtid 2, Base address 9000 */
> +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
> +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
> +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
> +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
> +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
> +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
> +
> +/* controller 1, Slot 1, tgtid 1, Base address a000 */
> +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
> +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
> +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
> +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
> +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
> +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
> +
> +#if defined(CONFIG_PCI)
> +#define CONFIG_NET_MULTI
> +#define CONFIG_PCI_PNP /* do pci plug-and-play */
> +
> +#undef CONFIG_EEPRO100
> +#undef CONFIG_TULIP
> +#undef CONFIG_RTL8139
> +
> +#ifdef CONFIG_RTL8139
> +/* This macro is used by RTL8139 but not defined in PPC architecture */
> +#define KSEG1ADDR(x) (x)
> +#define _IO_BASE 0x00000000
> +#endif
> +
> +
> +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> +#define CONFIG_DOS_PARTITION
> +
> +#endif /* CONFIG_PCI */
> +
> +/************************************************************
> + * USB support
> + ************************************************************/
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_USB
I like to see such lists sorted.
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_SETEXPR
I like to see such lists sorted.
> +#if defined(CONFIG_PCI)
> +#define CONFIG_CMD_PCI
> +#define CONFIG_CMD_BEDBUG
> +#define CONFIG_CMD_NET
> +#endif
> +
> +#undef CONFIG_WATCHDOG /* watchdog disabled */
> +
> +#define CONFIG_MMC 1
> +
> +#ifdef CONFIG_MMC
> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
I really don't like to see the same command definitions repeated (like
above for USB and here for MMC) and spread all over the file. I
understand your rationale, but I still consider it hard to read and to
maintain and thus bad style.
> +#define CONFIG_HOSTNAME unknown
Please do not do this. Either assign a reasonable name, or none at
all.
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
> + "loadaddr=1000000\0" \
> + "bootfile=uImage\0" \
> + "tftpflash=tftpboot $loadaddr $uboot; " \
> + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
> + "erase " MK_STR(TEXT_BASE) " +$filesize; " \
> + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
> + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
> + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Please use TABs for indentation.
> + "consoledev=ttyS0\0" \
> + "ramdiskaddr=2000000\0" \
> + "ramdiskfile=rootfs.ext2.gz.uboot\0" \
> + "fdtaddr=c00000\0" \
> + "fdtfile=p2020rdb.dtb\0" \
> + "bdev=sda1\0" \
> + "jffs2nor=mtdblock3\0" \
> + "norbootaddr=ef080000\0" \
> + "norfdtaddr=ef040000\0" \
> + "jffs2nand=mtdblock9\0" \
> + "nandbootaddr=100000\0" \
> + "nandfdtaddr=80000\0" \
> + "nandimgsize=400000\0" \
> + "nandfdtsize=80000\0" \
> + "usb_phy_type=ulpi\0" \
> + "vscfw_addr=ef000000\0" \
> + "othbootargs=ramdisk_size=600000\0" \
> + "usbfatboot=setenv bootargs root=/dev/ram rw " \
> + "console=$consoledev,$baudrate $othbootargs; " \
> + "usb start;" \
> + "fatload usb 0:2 $loadaddr $bootfile;" \
> + "fatload usb 0:2 $fdtaddr $fdtfile;" \
> + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
> + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
> + "usbext2boot=setenv bootargs root=/dev/ram rw " \
> + "console=$consoledev,$baudrate $othbootargs; " \
> + "usb start;" \
> + "ext2load usb 0:4 $loadaddr $bootfile;" \
> + "ext2load usb 0:4 $fdtaddr $fdtfile;" \
> + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
> + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
> + "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
> + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
> + "bootm $norbootaddr - $norfdtaddr\0" \
> + "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 "
> \
> + "console=$consoledev,$baudrate $othbootargs;" \
> + "nand read 2000000 $nandbootaddr $nandimgsize;" \
> + "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
> + "bootm 2000000 - 3000000;\0"
> +
> +
> +#define CONFIG_NFSBOOTCOMMAND \
> + "setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=$serverip:$rootpath " \
> + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> + "console=$consoledev,$baudrate $othbootargs;" \
> + "tftp $loadaddr $bootfile;" \
> + "tftp $fdtaddr $fdtfile;" \
> + "bootm $loadaddr - $fdtaddr"
> +
> +#define CONFIG_HDBOOT \
> + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
> + "console=$consoledev,$baudrate $othbootargs;" \
> + "usb start;" \
> + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
> + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
> + "bootm $loadaddr - $fdtaddr"
> +
> +#define CONFIG_RAMBOOTCOMMAND \
> + "setenv bootargs root=/dev/ram rw " \
> + "console=$consoledev,$baudrate $othbootargs; " \
> + "tftp $ramdiskaddr $ramdiskfile;" \
> + "tftp $loadaddr $bootfile;" \
> + "tftp $fdtaddr $fdtfile;" \
> + "bootm $loadaddr $ramdiskaddr $fdtaddr"
Maybe Freescale should come up with a common set of setting for all
(or at least many) boards, similar to what we have in
include/configs/amcc-common.h ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected]
"In Christianity neither morality nor religion come into contact with
reality at any point." - Friedrich Nietzsche
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