Since there is only one version of flushing the dcache for arm_cortex8, rename v7_flush_dcache_all to the the generic name flush_dcache. Because the function is intended for only omap3 boards, move the function to the new file cache_flush.S.
Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Dirk Behme <[email protected]> --- Changes in v2: Rebase against recent git head 3b9043a7c03290c9bdbef03848307263f5f3472c "omap3: bug fix for NOR boot support" This patch updates http://lists.denx.de/pipermail/u-boot/2009-July/055543.html Second patch of this series http://lists.denx.de/pipermail/u-boot/2009-July/055544.html seems to be fixed already, so doesn't seem to be necessary any more. Compile tested with ./MAKEALL ARM_CORTEX_A8, boot tested on BeagleBoard. cpu/arm_cortexa8/cpu.c | 2 cpu/arm_cortexa8/omap3/Makefile | 1 cpu/arm_cortexa8/omap3/board.c | 2 cpu/arm_cortexa8/omap3/cache_flush.S | 118 +++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/start.S | 86 ------------------------ include/asm-arm/arch-omap3/sys_proto.h | 2 6 files changed, 122 insertions(+), 89 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache_flush.S Index: u-boot-main/cpu/arm_cortexa8/cpu.c =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/cpu.c +++ u-boot-main/cpu/arm_cortexa8/cpu.c @@ -64,7 +64,7 @@ int cleanup_before_linux(void) /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ - v7_flush_dcache_all(get_device_type()); + flush_dcache(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ Index: u-boot-main/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-main/cpu/arm_cortexa8/omap3/board.c @@ -201,7 +201,7 @@ void s_init(void) * Right now flushing at low MPU speed. * Need to move after clock init */ - v7_flush_dcache_all(get_device_type()); + flush_dcache(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif Index: u-boot-main/cpu/arm_cortexa8/omap3/cache_flush.S =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/cache_flush.S @@ -0,0 +1,118 @@ +/* + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments <[email protected]> + * + * Copyright (c) 2001 Marius Gröger <[email protected]> + * Copyright (c) 2002 Alex Züpke <[email protected]> + * Copyright (c) 2002 Gary Jennejohn <[email protected]> + * Copyright (c) 2003 Richard Woodruff <[email protected]> + * Copyright (c) 2003 Kshitij <[email protected]> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * flush_dcache() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ + .align 5 +.global flush_dcache +flush_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mov r7, r0 @ take a backup of device type + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 +smi: .word 0x01600070 @ Call SMI monitor (smieq) + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + + Index: u-boot-main/cpu/arm_cortexa8/start.S =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/start.S +++ u-boot-main/cpu/arm_cortexa8/start.S @@ -414,89 +414,3 @@ fiq: bl do_fiq #endif - -/* - * v7_flush_dcache_all() - * - * Flush the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - * - * - mm - mm_struct describing address space - */ - .align 5 -.global v7_flush_dcache_all -v7_flush_dcache_all: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - mov r7, r0 @ take a backup of device type - cmp r0, #0x3 @ check if the device type is - @ GP - moveq r12, #0x1 @ set up to invalide L2 -smi: .word 0x01600070 @ Call SMI monitor (smieq) - cmp r7, #0x3 @ compare again in case its - @ lost - beq finished_inval @ if GP device, inval done - @ above - - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} Index: u-boot-main/cpu/arm_cortexa8/omap3/Makefile =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/omap3/Makefile +++ u-boot-main/cpu/arm_cortexa8/omap3/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o +SOBJS += cache_flush.o SOBJS += reset.o COBJS += board.o Index: u-boot-main/include/asm-arm/arch-omap3/sys_proto.h =================================================================== --- u-boot-main.orig/include/asm-arm/arch-omap3/sys_proto.h +++ u-boot-main/include/asm-arm/arch-omap3/sys_proto.h @@ -55,7 +55,7 @@ void secureworld_exit(void); void setup_auxcr(void); void try_unlock_memory(void); u32 get_boot_type(void); -void v7_flush_dcache_all(u32); +void flush_dcache(u32); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long);
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