> -----Original Message----- > From: Scott Wood [mailto:[email protected]] > Sent: Tuesday, August 18, 2009 11:12 AM > To: Paulraj, Sandeep > Cc: [email protected] > Subject: Re: [U-Boot] [PATCH] NAND: DaVinci: Adding 4 BIT ECC support > > On Tue, Aug 18, 2009 at 08:56:03AM -0500, Paulraj, Sandeep wrote: > > > > + case NAND_ECC_READSYN: > > > > + val = emif_regs->NAND4BITECC1; > > > > > > Use I/O accessors. > > I could not understand this one. It is done similarly > nand_davinci_enable_hwecc which is used for 1 BIT ECC. > > NANDFCR is a control register and we have to write the appropriate > valvue to it. > > We similarly write to other register that are part of the IP in other > sections of this driver. > > Well, the comment applies to the rest of the driver too. I won't NACK > because of it, but it's something to consider in the future. > > > I'll send in a patch with your comments addressed except the first one. > I can resend the patch( again if required) once I know what you mean by > your comment #1. > > What I mean is using accessors such as readl/writel -- though we're still > in a pretty sorry state with respect to what accessors we provide cross > architectures (you have to pick between native endian with no barriers, > or little endian with barriers).
Scott, I am quite certain that I have received comments for other patches that I have submitted earlier where I have been specifically been asked to do things the way I am doing at the moment and not use readl/writel(because of the reason you mentioned above). > > -Scott So should I assume that my updated patch has your ACK as you mentioned above that you want NACK it Thanks, Sandeep _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
