Hi Stefan, On Wed, Mar 16, 2016 at 12:14 AM, Stefan Roese <[email protected]> wrote: > This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, > installed on the congatec Qseven 2.0 evaluation carrier board > (conga-QEVAL). > > Its port is very similar to the MinnowboardMAX port and also uses > the Intel FSP as described in doc/README.x86. > > Currently supported are the following interfaces / devices: > - UART (via Winbond legacy SuperIO chip on carrier board) > - Ethernet (PCIe Intel I210 / E1000) > - SPI including SPI NOR as boot-device > - USB 2.0 > - SATA via U-Boot SCSI IF > - eMMC > - Video (HDMI output @ 800x600) > - PCIe >
Great job to support another x86 target! > Not supported yet is: > - I2C > - USB 3.0 > > Signed-off-by: Stefan Roese <[email protected]> > Cc: Simon Glass <[email protected]> > Cc: Bin Meng <[email protected]> > --- > arch/x86/Kconfig | 4 + > arch/x86/dts/Makefile | 1 + > arch/x86/dts/conga-qeval20-qa3-e3845.dts | 278 > +++++++++++++++++++++ > board/congatec/Kconfig | 29 +++ > board/congatec/conga-qeval20-qa3-e3845/Kconfig | 28 +++ > board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS | 7 + > board/congatec/conga-qeval20-qa3-e3845/Makefile | 7 + > .../conga-qeval20-qa3-e3845/conga-qeval20-qa3.c | 39 +++ > board/congatec/conga-qeval20-qa3-e3845/start.S | 9 + > configs/conga-qeval20-qa3-e3845_defconfig | 44 ++++ > include/configs/conga-qeval20-qa3-e3845.h | 67 +++++ > 11 files changed, 513 insertions(+) > create mode 100644 arch/x86/dts/conga-qeval20-qa3-e3845.dts > create mode 100644 board/congatec/Kconfig > create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Kconfig > create mode 100644 board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS > create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Makefile > create mode 100644 board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c > create mode 100644 board/congatec/conga-qeval20-qa3-e3845/start.S > create mode 100644 configs/conga-qeval20-qa3-e3845_defconfig > create mode 100644 include/configs/conga-qeval20-qa3-e3845.h > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index a0bd344..1400d9c 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -8,6 +8,9 @@ choice > prompt "Mainboard vendor" > default VENDOR_EMULATION > > +config VENDOR_CONGATEC > + bool "congatec" > + > config VENDOR_COREBOOT > bool "coreboot" > > @@ -26,6 +29,7 @@ config VENDOR_INTEL > endchoice > > # board-specific options below > +source "board/congatec/Kconfig" > source "board/coreboot/Kconfig" > source "board/efi/Kconfig" > source "board/emulation/Kconfig" > diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile > index 84feb19..5ca065d 100644 > --- a/arch/x86/dts/Makefile > +++ b/arch/x86/dts/Makefile > @@ -5,6 +5,7 @@ > dtb-y += bayleybay.dtb \ > chromebook_link.dtb \ > chromebox_panther.dtb \ > + conga-qeval20-qa3-e3845.dtb \ > cougarcanyon2.dtb \ > crownbay.dtb \ > efi.dtb \ > diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts > b/arch/x86/dts/conga-qeval20-qa3-e3845.dts > new file mode 100644 > index 0000000..478dece > --- /dev/null > +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts > @@ -0,0 +1,278 @@ > +/* > + * Copyright (C) 2014, Bin Meng <[email protected]> > + * Copyright (C) 2016 Stefan Roese <[email protected]> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/x86-gpio.h> > +#include <dt-bindings/interrupt-router/intel-irq.h> > + > +/include/ "skeleton.dtsi" > +/include/ "serial.dtsi" > +/include/ "rtc.dtsi" > +/include/ "tsc_timer.dtsi" > + > +/ { > + model = "congatec-QEVAL20-QA3-E3845"; > + compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; > + > + aliases { > + serial0 = &serial; > + spi0 = &spi; > + }; > + > + config { > + silent_console = <0>; > + }; > + > + pch_pinctrl { > + compatible = "intel,x86-pinctrl"; > + }; > + > + chosen { > + stdout-path = "/serial"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <0>; > + intel,apic-id = <0>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <1>; > + intel,apic-id = <2>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <2>; > + intel,apic-id = <4>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <3>; > + intel,apic-id = <6>; > + }; > + }; > + > + pci { > + compatible = "intel,pci-baytrail", "pci-x86"; > + #address-cells = <3>; > + #size-cells = <2>; > + u-boot,dm-pre-reloc; > + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 > + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 > + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; > + > + pch@1f,0 { > + reg = <0x0000f800 0 0 0 0>; > + compatible = "pci8086,0f1c", "intel,pch9"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + irq-router { > + compatible = "intel,irq-router"; > + intel,pirq-config = "ibase"; > + intel,ibase-offset = <0x50>; > + intel,pirq-link = <8 8>; > + intel,pirq-mask = <0xdee0>; > + intel,pirq-routing = < > + /* BayTrail PCI devices */ > + PCI_BDF(0, 2, 0) INTA PIRQA > + PCI_BDF(0, 3, 0) INTA PIRQA > + PCI_BDF(0, 16, 0) INTA PIRQA > + PCI_BDF(0, 17, 0) INTA PIRQA > + PCI_BDF(0, 18, 0) INTA PIRQA > + PCI_BDF(0, 19, 0) INTA PIRQA > + PCI_BDF(0, 20, 0) INTA PIRQA > + PCI_BDF(0, 21, 0) INTA PIRQA > + PCI_BDF(0, 22, 0) INTA PIRQA > + PCI_BDF(0, 23, 0) INTA PIRQA > + PCI_BDF(0, 24, 0) INTA PIRQA > + PCI_BDF(0, 24, 1) INTC PIRQC > + PCI_BDF(0, 24, 2) INTD PIRQD > + PCI_BDF(0, 24, 3) INTB PIRQB > + PCI_BDF(0, 24, 4) INTA PIRQA > + PCI_BDF(0, 24, 5) INTC PIRQC > + PCI_BDF(0, 24, 6) INTD PIRQD > + PCI_BDF(0, 24, 7) INTB PIRQB > + PCI_BDF(0, 26, 0) INTA PIRQA > + PCI_BDF(0, 27, 0) INTA PIRQA > + PCI_BDF(0, 28, 0) INTA PIRQA > + PCI_BDF(0, 28, 1) INTB PIRQB > + PCI_BDF(0, 28, 2) INTC PIRQC > + PCI_BDF(0, 28, 3) INTD PIRQD > + PCI_BDF(0, 29, 0) INTA PIRQA > + PCI_BDF(0, 30, 0) INTA PIRQA > + PCI_BDF(0, 30, 1) INTD PIRQD > + PCI_BDF(0, 30, 2) INTB PIRQB > + PCI_BDF(0, 30, 3) INTC PIRQC > + PCI_BDF(0, 30, 4) INTD PIRQD > + PCI_BDF(0, 30, 5) INTB PIRQB > + PCI_BDF(0, 31, 3) INTB PIRQB > + > + /* > + * PCIe root ports downstream > + * interrupts > + */ > + PCI_BDF(1, 0, 0) INTA PIRQA > + PCI_BDF(1, 0, 0) INTB PIRQB > + PCI_BDF(1, 0, 0) INTC PIRQC > + PCI_BDF(1, 0, 0) INTD PIRQD > + PCI_BDF(2, 0, 0) INTA PIRQB > + PCI_BDF(2, 0, 0) INTB PIRQC > + PCI_BDF(2, 0, 0) INTC PIRQD > + PCI_BDF(2, 0, 0) INTD PIRQA > + PCI_BDF(3, 0, 0) INTA PIRQC > + PCI_BDF(3, 0, 0) INTB PIRQD > + PCI_BDF(3, 0, 0) INTC PIRQA > + PCI_BDF(3, 0, 0) INTD PIRQB > + PCI_BDF(4, 0, 0) INTA PIRQD > + PCI_BDF(4, 0, 0) INTB PIRQA > + PCI_BDF(4, 0, 0) INTC PIRQB > + PCI_BDF(4, 0, 0) INTD PIRQC > + >; > + }; > + > + spi: spi { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "intel,ich9-spi"; > + spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0>; > + compatible = "stmicro,n25q064a", > + "spi-flash"; > + memory-map = <0xff800000 0x00800000>; > + rw-mrc-cache { > + label = "rw-mrc-cache"; > + reg = <0x006f0000 0x00010000>; > + }; > + }; > + }; > + > + gpioa { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0 0x20>; > + bank-name = "A"; > + }; > + > + gpiob { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x20 0x20>; > + bank-name = "B"; > + }; > + > + gpioc { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x40 0x20>; > + bank-name = "C"; > + }; > + > + gpiod { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x60 0x20>; > + bank-name = "D"; > + }; > + > + gpioe { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x80 0x20>; > + bank-name = "E"; > + }; > + > + gpiof { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0xA0 0x20>; > + bank-name = "F"; > + }; > + }; > + }; > + > + fsp { > + compatible = "intel,baytrail-fsp"; > + fsp,mrc-init-tseg-size = <0>; > + fsp,mrc-init-mmio-size = <0x800>; > + fsp,mrc-init-spd-addr1 = <0xa0>; > + fsp,mrc-init-spd-addr2 = <0xa2>; > + fsp,emmc-boot-mode = <2>; > + fsp,enable-sdio; > + fsp,enable-sdcard; > + fsp,enable-hsuart1; > + fsp,enable-spi; > + fsp,enable-sata; > + fsp,sata-mode = <1>; > + fsp,enable-lpe; > + fsp,lpss-sio-enable-pci-mode; > + fsp,enable-dma0; > + fsp,enable-dma1; > + fsp,enable-i2c0; > + fsp,enable-i2c1; > + fsp,enable-i2c2; > + fsp,enable-i2c3; > + fsp,enable-i2c4; > + fsp,enable-i2c5; > + fsp,enable-i2c6; > + fsp,enable-pwm0; > + fsp,enable-pwm1; > + fsp,igd-dvmt50-pre-alloc = <2>; > + fsp,aperture-size = <2>; > + fsp,gtt-size = <2>; > + fsp,scc-enable-pci-mode; > + fsp,os-selection = <4>; > + fsp,emmc45-ddr50-enabled; > + fsp,emmc45-retune-timer-value = <8>; > + fsp,enable-igd; > + fsp,enable-memory-down; > + fsp,memory-down-params { > + compatible = "intel,baytrail-fsp-mdp"; > + fsp,dram-speed = <2>; /* 2=1333MHz */ > + fsp,dram-type = <1>; /* 1=DDR3L */ > + fsp,dimm-0-enable; > + fsp,dimm-1-enable; > + fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ > + fsp,dimm-density = <2>; /* 2=4Gbit */ > + fsp,dimm-bus-width = <3>; /* 3=64bits */ > + fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b > */ > + > + /* These following values might need a re-visit */ > + fsp,dimm-tcl = <8>; > + fsp,dimm-trpt-rcd = <8>; > + fsp,dimm-twr = <8>; > + fsp,dimm-twtr = <4>; > + fsp,dimm-trrd = <6>; > + fsp,dimm-trtp = <4>; > + fsp,dimm-tfaw = <22>; > + }; > + }; > + > + microcode { > + update@0 { > +#include "microcode/m0130673322.dtsi" > + }; > + update@1 { > +#include "microcode/m0130679901.dtsi" > + }; > + }; > +}; > diff --git a/board/congatec/Kconfig b/board/congatec/Kconfig > new file mode 100644 > index 0000000..1dc306e > --- /dev/null > +++ b/board/congatec/Kconfig > @@ -0,0 +1,29 @@ > +# > +# Copyright (C) 2015, Bin Meng <[email protected]> > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +if VENDOR_CONGATEC > + > +choice > + prompt "Mainboard model" > + optional > + > +config TARGET_CONGA_QEVAL20_QA3_E3845 > + bool "congatec QEVAL 2.0 & conga-QA3/E3845" > + help > + This is the congatec Qseven 2.0 evaluation carrier board > + (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM. > + It contains an Atom E3845 with Ethernet, micro-SD, USB 2, > + USB 3, SATA, serial console and HDMI 1.3 video out. > + It requires some binary blobs - see README.x86 for details. > + > + Note that PCIE_ECAM_BASE is set up by the FSP so the value used > + by U-Boot matches that value. > + > +endchoice > + > +source "board/congatec/conga-qeval20-qa3-e3845/Kconfig" > + > +endif > diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig > b/board/congatec/conga-qeval20-qa3-e3845/Kconfig > new file mode 100644 > index 0000000..9f31238 > --- /dev/null > +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig > @@ -0,0 +1,28 @@ > +if TARGET_CONGA_QEVAL20_QA3_E3845 > + > +config SYS_BOARD > + default "conga-qeval20-qa3-e3845" > + > +config SYS_VENDOR > + default "congatec" > + > +config SYS_SOC > + default "baytrail" > + > +config SYS_CONFIG_NAME > + default "conga-qeval20-qa3-e3845" > + > +config SYS_TEXT_BASE > + default 0xfff00000 if !EFI_STUB > + default 0x01110000 if EFI_STUB > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select X86_RESET_VECTOR if !EFI_STUB > + select INTEL_BAYTRAIL > + select BOARD_ROMSIZE_KB_8192 > + > +config PCIE_ECAM_BASE > + default 0xe0000000 > + > +endif > diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS > b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS > new file mode 100644 > index 0000000..5a4d4dc > --- /dev/null > +++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS > @@ -0,0 +1,7 @@ > +congatec EVAL20-QA3-E3845 > +M: Stefan Roese <[email protected]> > +S: Maintained > +F: board/congatec/conga-qeval20-qa3-e3845 > +F: include/configs/conga-qeval20-qa3-e3845.h > +F: configs/conga-qeval20-qa3-e3845_defconfig > +F: arch/x86/dts/conga-qeval20-qa3-e3845.dts > diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile > b/board/congatec/conga-qeval20-qa3-e3845/Makefile > new file mode 100644 > index 0000000..23b8748 > --- /dev/null > +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile > @@ -0,0 +1,7 @@ > +# > +# Copyright (C) 2015, Google, Inc > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += conga-qeval20-qa3.o start.o > diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c > b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c > new file mode 100644 > index 0000000..ab6883e > --- /dev/null > +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c > @@ -0,0 +1,39 @@ > +/* > + * Copyright (C) 2016 Stefan Roese <[email protected]> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <winbond_w83627.h> > +#include <asm/gpio.h> > +#include <asm/ibmpc.h> > +#include <asm/pnp_def.h> > + > +int board_early_init_f(void) > +{ > + /* > + * The FSP enables the BayTrail internal legacy UART (again). > + * Disable it again, so that the Winbond one can be used. > + */ > + setup_internal_uart(0); > + > + /* Enable the legacy UART in the Winbond W83627 Super IO chip */ > + winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), > + UART0_BASE, UART0_IRQ); > + > + return 0; > +} > + > +int arch_early_init_r(void) > +{ > + /* do the pin-muxing */ > + gpio_ich6_pinctrl_init(); > + I guess this needs to be rebased on top of u-boot-x86/master. It won't compile as the following patches reworked the x86 pinctrl driver. http://patchwork.ozlabs.org/patch/596605/ http://patchwork.ozlabs.org/patch/596615/ > + return 0; > +} > + > +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) > +{ > + return; > +} This needs to be removed due to the pinctrl driver changes above. > diff --git a/board/congatec/conga-qeval20-qa3-e3845/start.S > b/board/congatec/conga-qeval20-qa3-e3845/start.S > new file mode 100644 > index 0000000..2c941a4 > --- /dev/null > +++ b/board/congatec/conga-qeval20-qa3-e3845/start.S > @@ -0,0 +1,9 @@ > +/* > + * Copyright (C) 2015, Google, Inc > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +.globl early_board_init > +early_board_init: > + jmp early_board_init_ret > diff --git a/configs/conga-qeval20-qa3-e3845_defconfig > b/configs/conga-qeval20-qa3-e3845_defconfig > new file mode 100644 > index 0000000..714dead > --- /dev/null > +++ b/configs/conga-qeval20-qa3-e3845_defconfig > @@ -0,0 +1,44 @@ > +CONFIG_X86=y > +CONFIG_VENDOR_CONGATEC=y > +CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y > +CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845" > +CONFIG_HAVE_INTEL_ME=y > +CONFIG_ENABLE_MRC_CACHE=y > +CONFIG_SMP=y > +CONFIG_HAVE_VGA_BIOS=y > +CONFIG_GENERATE_PIRQ_TABLE=y > +CONFIG_GENERATE_MP_TABLE=y > +CONFIG_FIT=y > +CONFIG_FIT_SIGNATURE=y > +CONFIG_BOOTSTAGE=y > +CONFIG_BOOTSTAGE_REPORT=y > +CONFIG_CMD_CPU=y > +# CONFIG_CMD_IMLS is not set > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPIO=y > +# CONFIG_CMD_SETEXPR is not set > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_BOOTSTAGE=y > +CONFIG_OF_CONTROL=y > +CONFIG_CPU=y > +CONFIG_WINBOND_W83627=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_DM_ETH=y > +CONFIG_DM_PCI=y > +CONFIG_DM_RTC=y > +CONFIG_DEBUG_UART=y > +CONFIG_DEBUG_UART_BASE=0x3f8 > +CONFIG_DEBUG_UART_CLOCK=1843200 > +CONFIG_SYS_NS16550=y > +CONFIG_ICH_SPI=y > +CONFIG_TIMER=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_VIDEO_VESA=y > +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y > +CONFIG_FRAMEBUFFER_VESA_MODE_114=y > +CONFIG_USE_PRIVATE_LIBGCC=y > diff --git a/include/configs/conga-qeval20-qa3-e3845.h > b/include/configs/conga-qeval20-qa3-e3845.h > new file mode 100644 > index 0000000..fabaf2a > --- /dev/null > +++ b/include/configs/conga-qeval20-qa3-e3845.h > @@ -0,0 +1,67 @@ > +/* > + * Copyright (C) 2016 Stefan Roese <[email protected]> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/* > + * board/config.h - configuration options, board specific > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <configs/x86-common.h> > + > +#define CONFIG_SYS_MONITOR_LEN (1 << 20) > +#define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_ARCH_EARLY_INIT_R > +#define CONFIG_ARCH_MISC_INIT > + > +#define CONFIG_WINBOND I believe this one needs to be dropped. > + > +#define CONFIG_PCI_PNP > +#define CONFIG_E1000 This one should go to board defconfig file. > +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ > + "stdout=serial\0" \ > + "stderr=serial\0" > + > +#define CONFIG_SCSI_DEV_LIST \ > + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ > + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} > + > +#define CONFIG_MMC > +#define CONFIG_SDHCI > +#define CONFIG_GENERIC_MMC > +#define CONFIG_MMC_SDMA > +#define CONFIG_CMD_MMC > + > +#undef CONFIG_USB_MAX_CONTROLLER_COUNT > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > + > +#define VIDEO_IO_OFFSET 0 > +#define CONFIG_X86EMU_RAW_IO > +#define CONFIG_CMD_BMP > + > +#define CONFIG_ENV_SECT_SIZE 0x1000 > +#define CONFIG_ENV_OFFSET 0x007fe000 > + > +#undef CONFIG_BOOTARGS > +#undef CONFIG_BOOTCOMMAND > + > +#define CONFIG_BOOTARGS \ > + "root=/dev/sda1 ro quiet" > +#define CONFIG_BOOTCOMMAND \ > + "load scsi 0:1 03000000 /boot/vmlinuz-4.2.0-26-generic;" \ > + "load scsi 0:1 04000000 /boot/initrd.img-4.2.0-26-generic;" \ > + "run boot" > + > +#undef CONFIG_EXTRA_ENV_SETTINGS > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ > + "upd_uboot=tftp 100000 conga/u-boot.rom;" \ > + "sf probe;sf update 100000 0 7fe000\0" > + > +#define CONFIG_PREBOOT > + > +#endif /* __CONFIG_H */ > -- Regards, Bin _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
