On 04/18/2016 08:36 PM, Huan Wang wrote: > Hi, York, > >> On 03/28/2016 02:16 PM, Ed Swarthout wrote: >>> When switching between the early and final mmu tables, the stack will >>> get corrupted if the Non-Secure attribute is different. For ls1043a, >>> this issue is currently masked because flush_dcache_all is called >>> before the switch when CONFIG_SYS_DPAA_FMAN is defined. >>> >>> Signed-off-by: Ed Swarthout <[email protected]> >>> --- >>> >>> Resend to fix diff format. >>> >>> denx/master with CONFIG_SYS_DPAA_FMAN undefined: >>> Fixes: >>> >>> U-Boot 2016.03-00530-g1fee6de (Mar 28 2016 - 13:46:36 -0500) >>> SoC: LS1043E (0x87920010) >>> ... >>> Detected UDIMM 18ASF1G72AZ-2G1A1 >>> 4 GiB (DDR4, 32-bit, CL=11, ECC on) >>> DDR Chip-Select Interleaving Mode: CS0+CS1 "Synchronous Abort" >>> handler, esr 0x8a000000 >>> ELR: deadbeefdeadbeef >>> LR: deadbeefdeadbeef >>> x0 : 000000ff440c0400 x1 : 0000000000022518 >>> x2 : 0000000000000040 x3 : 000000000000003f >>> x4 : 0000000000000004 x5 : 0000000000000001 >>> x6 : 0000000900000000 x7 : 0000000000200000 >>> x8 : 0000000000000015 x9 : 000000000000000c >>> x10: 0000000000000401 x11: 00000008ffe06000 >>> x12: 00000000000001ff x13: 0000000040000000 >>> x14: 0000000000200000 x15: 0000000000000001 >>> x16: 0000000000000000 x17: 0000000000000002 >>> x18: 00000000ffdd8d78 x19: deadbeefdeadbeef >>> x20: deadbeefdeadbeef x21: deadbeefdeadbeef >>> x22: deadbeefdeadbeef x23: deadbeefdeadbeef >>> x24: deadbeefdeadbeef x25: deadbeefdeadbeef >>> x26: deadbeefdeadbeef x27: 0000000000000000 >>> x28: 00000000fff6ca90 x29: deadbeefdeadbeef >>> >>> >>> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++---- >>> 1 file changed, 8 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >>> b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >>> index 42ca7df..1f5842a 100644 >>> --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >>> @@ -159,9 +159,11 @@ static const struct sys_mmu_table >> early_mmu_table[] = { >>> { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, >>> CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, >>> { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, >>> - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, >>> + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, >>> + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, >>> { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, >>> - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, >>> + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, >>> + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, >>> #endif >>> }; >>> >>> @@ -247,7 +249,8 @@ static const struct sys_mmu_table final_mmu_table[] >> = { >>> CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, >>> PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, >>> { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, >>> - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, >>> + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, >>> + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, >>> { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, >>> CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, >>> PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -258,7 >>> +261,8 @@ static const struct sys_mmu_table final_mmu_table[] = { >>> CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, >>> PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, >>> { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, >>> - CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, >>> + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, >>> + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, >>> #endif >>> }; >>> #endif >>> >> >> Alison/Qianyu, >> >> This change looks right to me. Please see if if flushing can be removed. >> > [Alison Wang] I verified flushing can be removed. >
Thanks. Please submit a patch to remove the unnecessary flushing. York _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
