From: Prabhakar Kushwaha:
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> unsigned int cpu;
> + unsigned int svr, ver;
> const u8 core_cplx_pll[8] = {
...
> - FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> + svr = gur_in32(&gur->svr);
> + ver = SVR_SOC_VER(svr);
> + if (ver == SVR_LS1012) {
> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> + } else {
> + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
Why introduce a run-time check for every board when this could be handled at
compile time?
Ed
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