Hi Tom,
this PR contains some fixes for the MIPS cache code. I've also applied the PIC32
SPI driver because there is no reaction from Jagan and the change is isolated.
Please pull, thanks.
The following changes since commit 6b3943f1b04be60f147ee540fbd72c4c7ea89f80:
siemens,am33x: add draco etamin board (2016-06-09 13:53:13 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
for you to fetch changes up to e19b9004575cacf1f64fff894621adafe0e7ea7f:
spi: pic32_spi: add SPI master driver for PIC32 SoC. (2016-06-10 12:31:12
+0200)
----------------------------------------------------------------
Paul Burton (2):
MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex
Purna Chandra Mandal (1):
spi: pic32_spi: add SPI master driver for PIC32 SoC.
arch/mips/Kconfig | 2 +-
arch/mips/lib/cache.c | 2 +-
drivers/spi/Kconfig | 8 +++
drivers/spi/Makefile | 1 +
drivers/spi/pic32_spi.c | 448
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 459 insertions(+), 2 deletions(-)
create mode 100644 drivers/spi/pic32_spi.c
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