Do the same WEIM initialization as done in the Linux kernel
according to arch/arm/boot/dts/imx6qdl-sabreauto.dtsi from kernel 4.9.
Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 5fca4d1..13a9b5a 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -221,12 +221,20 @@ static void eimnor_cs_setup(void)
{
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
- writel(0x00020181, &weim_regs->cs0gcr1);
+ /*
+ * Configure weim like the linux kernel.
+ * From arch/arm/boot/dts/imx6qdl-sabreauto.dtsi:
+ *
+ * fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ * 0x0000c000 0x1404a38e 0x00000000>;
+ */
+
+ writel(0x00620081, &weim_regs->cs0gcr1);
writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x1c022000, &weim_regs->cs0rcr1);
writel(0x0000c000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000120, &weim_regs->wcr);
+ writel(0x1404a38e, &weim_regs->cs0wcr1);
+ writel(0x00000000, &weim_regs->wcr);
set_chipselect_size(CS0_128);
}
--
2.7.4
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