To ensure compatibility with all PHYs, we need to keep the MDIO clock (MDC) below 2.5MHz (the guaranteed operating limit from IEEE 802.3), even if some PHYs will tolerate higher speeds.
This changeset also cleans up the MDIO read/write functions by removing pointless bit-masking in a variable initialised to 0. Philipp Tomsich (2): sun8i_emac: Set MDC divider for MDIO read/write sun8i_emac: remove unnecessary bit-masking for mdio_read/write drivers/net/sun8i_emac.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
