On 02/23/2017 02:27 AM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination and move existing register > space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, > so that it can be used for both chasis 2 and chasis 3. > > Signed-off-by: Prabhakar Kushwaha <[email protected]> > Signed-off-by: Ashish Kumar <[email protected]> > --- > v2: > Add new Kconfig in alphabetic order > > README | 9 ++++ > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++ > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 -------------------- > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > include/fsl_immap.h | 51 > ++++++++++++++++++++++ > 7 files changed, 69 insertions(+), 48 deletions(-) >
<snip> > #define SMMU_SCR1 (SMMU_BASE + 0x4) > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > index 0678fba..04add3b 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > @@ -10,6 +10,7 @@ > #define __ARCH_FSL_LSCH3_IMMAP_H_ > > #define CONFIG_SYS_IMMR 0x01000000 > +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + > 0x3090000) Can you move this macro to Kconfig and clean up existing use? York _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
