On 02/23/2017 02:27 AM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination and move existing register > space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, > so that it can be used for both chasis 2 and chasis 3. >
All of your patches have the (sometime inconsistent) indentation in commit message. Please fix. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
